LED001_CM4.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 00000000 00000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000026ac 10000000 10000000 00002000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .startup_copro_fw.Reset_Handler 00000050 100026ac 100026ac 000046ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 3 .rodata 00000000 100026fc 100026fc 0000500c 2**0 CONTENTS, ALLOC, LOAD, DATA 4 .ARM.extab 00000000 100026fc 100026fc 0000500c 2**0 CONTENTS, READONLY 5 .ARM 00000000 100026fc 100026fc 0000500c 2**0 CONTENTS, READONLY 6 .preinit_array 00000000 100026fc 100026fc 0000500c 2**0 CONTENTS, ALLOC, LOAD, DATA 7 .init_array 00000004 100026fc 100026fc 000046fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .fini_array 00000004 10002700 10002700 00004700 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 9 .data 0000000c 10020000 10002704 00005000 2**2 CONTENTS, ALLOC, LOAD, DATA 10 .resource_table 00000000 1002000c 1002000c 0000500c 2**0 CONTENTS 11 .bss 00000020 1002000c 10002710 0000500c 2**2 ALLOC 12 ._user_heap_stack 00000604 1002002c 10002730 0000500c 2**0 ALLOC 13 .ARM.attributes 00000030 00000000 00000000 0000500c 2**0 CONTENTS, READONLY 14 .debug_info 000083c7 00000000 00000000 0000503c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_abbrev 00001139 00000000 00000000 0000d403 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_aranges 000005a0 00000000 00000000 0000e540 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_rnglists 00000422 00000000 00000000 0000eae0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_macro 00042d54 00000000 00000000 0000ef02 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line 000074ad 00000000 00000000 00051c56 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_str 001bccc5 00000000 00000000 00059103 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .comment 00000043 00000000 00000000 00215dc8 2**0 CONTENTS, READONLY 22 .debug_frame 00001500 00000000 00000000 00215e0c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 23 .debug_line_str 00000056 00000000 00000000 0021730c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 10000000 <__do_global_dtors_aux>: 10000000: b510 push {r4, lr} 10000002: 4c05 ldr r4, [pc, #20] @ (10000018 <__do_global_dtors_aux+0x18>) 10000004: 7823 ldrb r3, [r4, #0] 10000006: b933 cbnz r3, 10000016 <__do_global_dtors_aux+0x16> 10000008: 4b04 ldr r3, [pc, #16] @ (1000001c <__do_global_dtors_aux+0x1c>) 1000000a: b113 cbz r3, 10000012 <__do_global_dtors_aux+0x12> 1000000c: 4804 ldr r0, [pc, #16] @ (10000020 <__do_global_dtors_aux+0x20>) 1000000e: f3af 8000 nop.w 10000012: 2301 movs r3, #1 10000014: 7023 strb r3, [r4, #0] 10000016: bd10 pop {r4, pc} 10000018: 1002000c .word 0x1002000c 1000001c: 00000000 .word 0x00000000 10000020: 10002694 .word 0x10002694 10000024 : 10000024: b508 push {r3, lr} 10000026: 4b03 ldr r3, [pc, #12] @ (10000034 ) 10000028: b11b cbz r3, 10000032 1000002a: 4903 ldr r1, [pc, #12] @ (10000038 ) 1000002c: 4803 ldr r0, [pc, #12] @ (1000003c ) 1000002e: f3af 8000 nop.w 10000032: bd08 pop {r3, pc} 10000034: 00000000 .word 0x00000000 10000038: 10020010 .word 0x10020010 1000003c: 10002694 .word 0x10002694 10000040 : * configuration. * @param None * @retval None */ void SystemInit (void) { 10000040: b480 push {r7} 10000042: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if defined (CORE_CM4) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 10000044: 4b0f ldr r3, [pc, #60] @ (10000084 ) 10000046: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 1000004a: 4a0e ldr r2, [pc, #56] @ (10000084 ) 1000004c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 10000050: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined (VECT_TAB_SRAM) SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* Disable all interrupts and events */ CLEAR_REG(EXTI_C2->IMR1); 10000054: 4b0c ldr r3, [pc, #48] @ (10000088 ) 10000056: 2200 movs r2, #0 10000058: 601a str r2, [r3, #0] CLEAR_REG(EXTI_C2->IMR2); 1000005a: 4b0b ldr r3, [pc, #44] @ (10000088 ) 1000005c: 2200 movs r2, #0 1000005e: 611a str r2, [r3, #16] CLEAR_REG(EXTI_C2->IMR3); 10000060: 4b09 ldr r3, [pc, #36] @ (10000088 ) 10000062: 2200 movs r2, #0 10000064: 621a str r2, [r3, #32] CLEAR_REG(EXTI_C2->EMR1); 10000066: 4b08 ldr r3, [pc, #32] @ (10000088 ) 10000068: 2200 movs r2, #0 1000006a: 605a str r2, [r3, #4] CLEAR_REG(EXTI_C2->EMR2); 1000006c: 4b06 ldr r3, [pc, #24] @ (10000088 ) 1000006e: 2200 movs r2, #0 10000070: 615a str r2, [r3, #20] CLEAR_REG(EXTI_C2->EMR3); 10000072: 4b05 ldr r3, [pc, #20] @ (10000088 ) 10000074: 2200 movs r2, #0 10000076: 625a str r2, [r3, #36] @ 0x24 #else #error Please #define CORE_CM4 #endif } 10000078: bf00 nop 1000007a: 46bd mov sp, r7 1000007c: f85d 7b04 ldr.w r7, [sp], #4 10000080: 4770 bx lr 10000082: bf00 nop 10000084: e000ed00 .word 0xe000ed00 10000088: 5000d0c0 .word 0x5000d0c0 1000008c
: /** * @brief The application entry point. * @retval int */ int main(void) { 1000008c: b580 push {r7, lr} 1000008e: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 10000090: f000 f94e bl 10000330 /* USER CODE BEGIN Init */ /* USER CODE END Init */ if(IS_ENGINEERING_BOOT_MODE()) 10000094: 4b0e ldr r3, [pc, #56] @ (100000d0 ) 10000096: 681b ldr r3, [r3, #0] 10000098: f003 0307 and.w r3, r3, #7 1000009c: 2b04 cmp r3, #4 1000009e: d101 bne.n 100000a4 { /* Configure the system clock */ SystemClock_Config(); 100000a0: f000 f81a bl 100000d8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 100000a4: f000 f8b0 bl 10000208 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, GPIO_PIN_RESET); 100000a8: 2200 movs r2, #0 100000aa: 2180 movs r1, #128 @ 0x80 100000ac: 4809 ldr r0, [pc, #36] @ (100000d4 ) 100000ae: f000 fc8f bl 100009d0 HAL_Delay(1000); 100000b2: f44f 707a mov.w r0, #1000 @ 0x3e8 100000b6: f000 f9ab bl 10000410 HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, GPIO_PIN_SET); 100000ba: 2201 movs r2, #1 100000bc: 2180 movs r1, #128 @ 0x80 100000be: 4805 ldr r0, [pc, #20] @ (100000d4 ) 100000c0: f000 fc86 bl 100009d0 HAL_Delay(1000); 100000c4: f44f 707a mov.w r0, #1000 @ 0x3e8 100000c8: f000 f9a2 bl 10000410 HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, GPIO_PIN_RESET); 100000cc: bf00 nop 100000ce: e7eb b.n 100000a8 100000d0: 50020000 .word 0x50020000 100000d4: 50004000 .word 0x50004000 100000d8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 100000d8: b580 push {r7, lr} 100000da: b0d2 sub sp, #328 @ 0x148 100000dc: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 100000de: f507 73a4 add.w r3, r7, #328 @ 0x148 100000e2: f5a3 738a sub.w r3, r3, #276 @ 0x114 100000e6: 4618 mov r0, r3 100000e8: f44f 738a mov.w r3, #276 @ 0x114 100000ec: 461a mov r2, r3 100000ee: 2100 movs r1, #0 100000f0: f002 faa4 bl 1000263c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 100000f4: f507 73a4 add.w r3, r7, #328 @ 0x148 100000f8: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100000fc: 4618 mov r0, r3 100000fe: 2330 movs r3, #48 @ 0x30 10000100: 461a mov r2, r3 10000102: 2100 movs r1, #0 10000104: f002 fa9a bl 1000263c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 10000108: f507 73a4 add.w r3, r7, #328 @ 0x148 1000010c: f5a3 738a sub.w r3, r3, #276 @ 0x114 10000110: 2202 movs r2, #2 10000112: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 10000114: f507 73a4 add.w r3, r7, #328 @ 0x148 10000118: f5a3 738a sub.w r3, r3, #276 @ 0x114 1000011c: 2201 movs r2, #1 1000011e: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1; 10000120: f507 73a4 add.w r3, r7, #328 @ 0x148 10000124: f5a3 738a sub.w r3, r3, #276 @ 0x114 10000128: 2200 movs r2, #0 1000012a: 615a str r2, [r3, #20] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 1000012c: f507 73a4 add.w r3, r7, #328 @ 0x148 10000130: f5a3 738a sub.w r3, r3, #276 @ 0x114 10000134: 2200 movs r2, #0 10000136: 625a str r2, [r3, #36] @ 0x24 RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; 10000138: f507 73a4 add.w r3, r7, #328 @ 0x148 1000013c: f5a3 738a sub.w r3, r3, #276 @ 0x114 10000140: 2200 movs r2, #0 10000142: 661a str r2, [r3, #96] @ 0x60 RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; 10000144: f507 73a4 add.w r3, r7, #328 @ 0x148 10000148: f5a3 738a sub.w r3, r3, #276 @ 0x114 1000014c: 2200 movs r2, #0 1000014e: f8c3 209c str.w r2, [r3, #156] @ 0x9c RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; 10000152: f507 73a4 add.w r3, r7, #328 @ 0x148 10000156: f5a3 738a sub.w r3, r3, #276 @ 0x114 1000015a: 2200 movs r2, #0 1000015c: f8c3 20d8 str.w r2, [r3, #216] @ 0xd8 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 10000160: f107 0334 add.w r3, r7, #52 @ 0x34 10000164: 4618 mov r0, r3 10000166: f000 fc4d bl 10000a04 1000016a: 4603 mov r3, r0 1000016c: 2b00 cmp r3, #0 1000016e: d001 beq.n 10000174 { Error_Handler(); 10000170: f000 f872 bl 10000258 } /** RCC Clock Config */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK 10000174: f507 73a4 add.w r3, r7, #328 @ 0x148 10000178: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 1000017c: 22fe movs r2, #254 @ 0xfe 1000017e: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4 |RCC_CLOCKTYPE_PCLK5; RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_HSI; 10000180: f507 73a4 add.w r3, r7, #328 @ 0x148 10000184: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 10000188: 2200 movs r2, #0 1000018a: 60da str r2, [r3, #12] RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1; 1000018c: f507 73a4 add.w r3, r7, #328 @ 0x148 10000190: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 10000194: 2200 movs r2, #0 10000196: 611a str r2, [r3, #16] RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_HSI; 10000198: f507 73a4 add.w r3, r7, #328 @ 0x148 1000019c: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001a0: 2200 movs r2, #0 100001a2: 615a str r2, [r3, #20] RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1; 100001a4: f507 73a4 add.w r3, r7, #328 @ 0x148 100001a8: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001ac: 2200 movs r2, #0 100001ae: 619a str r2, [r3, #24] RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV1; 100001b0: f507 73a4 add.w r3, r7, #328 @ 0x148 100001b4: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001b8: 2200 movs r2, #0 100001ba: 61da str r2, [r3, #28] RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV1; 100001bc: f507 73a4 add.w r3, r7, #328 @ 0x148 100001c0: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001c4: 2200 movs r2, #0 100001c6: 621a str r2, [r3, #32] RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV1; 100001c8: f507 73a4 add.w r3, r7, #328 @ 0x148 100001cc: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001d0: 2200 movs r2, #0 100001d2: 625a str r2, [r3, #36] @ 0x24 RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV1; 100001d4: f507 73a4 add.w r3, r7, #328 @ 0x148 100001d8: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001dc: 2200 movs r2, #0 100001de: 629a str r2, [r3, #40] @ 0x28 RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV1; 100001e0: f507 73a4 add.w r3, r7, #328 @ 0x148 100001e4: f5a3 73a2 sub.w r3, r3, #324 @ 0x144 100001e8: 2200 movs r2, #0 100001ea: 62da str r2, [r3, #44] @ 0x2c if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) 100001ec: 1d3b adds r3, r7, #4 100001ee: 4618 mov r0, r3 100001f0: f001 f9a6 bl 10001540 100001f4: 4603 mov r3, r0 100001f6: 2b00 cmp r3, #0 100001f8: d001 beq.n 100001fe { Error_Handler(); 100001fa: f000 f82d bl 10000258 } } 100001fe: bf00 nop 10000200: f507 77a4 add.w r7, r7, #328 @ 0x148 10000204: 46bd mov sp, r7 10000206: bd80 pop {r7, pc} 10000208 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 10000208: b580 push {r7, lr} 1000020a: b086 sub sp, #24 1000020c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 1000020e: 1d3b adds r3, r7, #4 10000210: 2200 movs r2, #0 10000212: 601a str r2, [r3, #0] 10000214: 605a str r2, [r3, #4] 10000216: 609a str r2, [r3, #8] 10000218: 60da str r2, [r3, #12] 1000021a: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 1000021c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000220: 2204 movs r2, #4 10000222: f8c3 2aa8 str.w r2, [r3, #2728] @ 0xaa8 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, GPIO_PIN_RESET); 10000226: 2200 movs r2, #0 10000228: 2180 movs r1, #128 @ 0x80 1000022a: 480a ldr r0, [pc, #40] @ (10000254 ) 1000022c: f000 fbd0 bl 100009d0 /*Configure GPIO pin : PC7 */ GPIO_InitStruct.Pin = GPIO_PIN_7; 10000230: 2380 movs r3, #128 @ 0x80 10000232: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 10000234: 2301 movs r3, #1 10000236: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 10000238: 2300 movs r3, #0 1000023a: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 1000023c: 2300 movs r3, #0 1000023e: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 10000240: 1d3b adds r3, r7, #4 10000242: 4619 mov r1, r3 10000244: 4803 ldr r0, [pc, #12] @ (10000254 ) 10000246: f000 fa19 bl 1000067c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 1000024a: bf00 nop 1000024c: 3718 adds r7, #24 1000024e: 46bd mov sp, r7 10000250: bd80 pop {r7, pc} 10000252: bf00 nop 10000254: 50004000 .word 0x50004000 10000258 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 10000258: b480 push {r7} 1000025a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 1000025c: b672 cpsid i } 1000025e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 10000260: bf00 nop 10000262: e7fd b.n 10000260 10000264 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 10000264: b580 push {r7, lr} 10000266: af00 add r7, sp, #0 /* USER CODE END MspInit 0 */ /* System interrupt init*/ /* MemoryManagement_IRQn interrupt configuration */ HAL_NVIC_SetPriority(MemoryManagement_IRQn, 1, 0); 10000268: 2200 movs r2, #0 1000026a: 2101 movs r1, #1 1000026c: f06f 000b mvn.w r0, #11 10000270: f000 f9cd bl 1000060e /* BusFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(BusFault_IRQn, 1, 0); 10000274: 2200 movs r2, #0 10000276: 2101 movs r1, #1 10000278: f06f 000a mvn.w r0, #10 1000027c: f000 f9c7 bl 1000060e /* UsageFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(UsageFault_IRQn, 1, 0); 10000280: 2200 movs r2, #0 10000282: 2101 movs r1, #1 10000284: f06f 0009 mvn.w r0, #9 10000288: f000 f9c1 bl 1000060e /* SVCall_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SVCall_IRQn, 1, 0); 1000028c: 2200 movs r2, #0 1000028e: 2101 movs r1, #1 10000290: f06f 0004 mvn.w r0, #4 10000294: f000 f9bb bl 1000060e /* DebugMonitor_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DebugMonitor_IRQn, 1, 0); 10000298: 2200 movs r2, #0 1000029a: 2101 movs r1, #1 1000029c: f06f 0003 mvn.w r0, #3 100002a0: f000 f9b5 bl 1000060e /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 1, 0); 100002a4: 2200 movs r2, #0 100002a6: 2101 movs r1, #1 100002a8: f06f 0001 mvn.w r0, #1 100002ac: f000 f9af bl 1000060e /* Peripheral interrupt init */ /* RCC_WAKEUP_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0); 100002b0: 2200 movs r2, #0 100002b2: 2100 movs r1, #0 100002b4: 2091 movs r0, #145 @ 0x91 100002b6: f000 f9aa bl 1000060e HAL_NVIC_EnableIRQ(RCC_WAKEUP_IRQn); 100002ba: 2091 movs r0, #145 @ 0x91 100002bc: f000 f9c3 bl 10000646 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 100002c0: bf00 nop 100002c2: bd80 pop {r7, pc} 100002c4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 100002c4: b480 push {r7} 100002c6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 100002c8: bf00 nop 100002ca: e7fd b.n 100002c8 100002cc : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 100002cc: b480 push {r7} 100002ce: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 100002d0: bf00 nop 100002d2: e7fd b.n 100002d0 100002d4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 100002d4: b480 push {r7} 100002d6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 100002d8: bf00 nop 100002da: e7fd b.n 100002d8 100002dc : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 100002dc: b480 push {r7} 100002de: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 100002e0: bf00 nop 100002e2: e7fd b.n 100002e0 100002e4 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 100002e4: b480 push {r7} 100002e6: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 100002e8: bf00 nop 100002ea: e7fd b.n 100002e8 100002ec : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 100002ec: b480 push {r7} 100002ee: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 100002f0: bf00 nop 100002f2: 46bd mov sp, r7 100002f4: f85d 7b04 ldr.w r7, [sp], #4 100002f8: 4770 bx lr 100002fa : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 100002fa: b480 push {r7} 100002fc: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 100002fe: bf00 nop 10000300: 46bd mov sp, r7 10000302: f85d 7b04 ldr.w r7, [sp], #4 10000306: 4770 bx lr 10000308 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 10000308: b480 push {r7} 1000030a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 1000030c: bf00 nop 1000030e: 46bd mov sp, r7 10000310: f85d 7b04 ldr.w r7, [sp], #4 10000314: 4770 bx lr 10000316 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 10000316: b580 push {r7, lr} 10000318: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 1000031a: f000 f859 bl 100003d0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 1000031e: bf00 nop 10000320: bd80 pop {r7, pc} 10000322 : /** * @brief This function handles RCC wake-up interrupt. */ void RCC_WAKEUP_IRQHandler(void) { 10000322: b580 push {r7, lr} 10000324: af00 add r7, sp, #0 /* USER CODE BEGIN RCC_WAKEUP_IRQn 0 */ /* USER CODE END RCC_WAKEUP_IRQn 0 */ HAL_RCC_WAKEUP_IRQHandler(); 10000326: f001 fd29 bl 10001d7c /* USER CODE BEGIN RCC_WAKEUP_IRQn 1 */ /* USER CODE END RCC_WAKEUP_IRQn 1 */ } 1000032a: bf00 nop 1000032c: bd80 pop {r7, pc} 1000032e : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 1000032e: e7fe b.n 1000032e 10000330 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 10000330: b580 push {r7, lr} 10000332: af00 add r7, sp, #0 /* Set Interrupt Group Priority */ #if defined (CORE_CM4) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 10000334: 2003 movs r0, #3 10000336: f000 f95f bl 100005f8 #endif /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); 1000033a: f001 fcde bl 10001cfa 1000033e: 4603 mov r3, r0 10000340: 4a07 ldr r2, [pc, #28] @ (10000360 ) 10000342: 6013 str r3, [r2, #0] /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 10000344: 200f movs r0, #15 10000346: f000 f80d bl 10000364 1000034a: 4603 mov r3, r0 1000034c: 2b00 cmp r3, #0 1000034e: d001 beq.n 10000354 { return HAL_ERROR; 10000350: 2301 movs r3, #1 10000352: e002 b.n 1000035a } /* Init the low level hardware */ HAL_MspInit(); 10000354: f7ff ff86 bl 10000264 /* Return function status */ return HAL_OK; 10000358: 2300 movs r3, #0 } 1000035a: 4618 mov r0, r3 1000035c: bd80 pop {r7, pc} 1000035e: bf00 nop 10000360: 10020000 .word 0x10020000 10000364 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 10000364: b580 push {r7, lr} 10000366: b082 sub sp, #8 10000368: af00 add r7, sp, #0 1000036a: 6078 str r0, [r7, #4] #endif /* CORE_CA7 */ #if defined (CORE_CM4) if ((uint32_t)uwTickFreq == 0U) 1000036c: 4b15 ldr r3, [pc, #84] @ (100003c4 ) 1000036e: 781b ldrb r3, [r3, #0] 10000370: 2b00 cmp r3, #0 10000372: d101 bne.n 10000378 { return HAL_ERROR; 10000374: 2301 movs r3, #1 10000376: e021 b.n 100003bc } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock /(1000U / uwTickFreq)) > 0U) 10000378: 4b13 ldr r3, [pc, #76] @ (100003c8 ) 1000037a: 681a ldr r2, [r3, #0] 1000037c: 4b11 ldr r3, [pc, #68] @ (100003c4 ) 1000037e: 781b ldrb r3, [r3, #0] 10000380: 4619 mov r1, r3 10000382: f44f 737a mov.w r3, #1000 @ 0x3e8 10000386: fbb3 f3f1 udiv r3, r3, r1 1000038a: fbb2 f3f3 udiv r3, r2, r3 1000038e: 4618 mov r0, r3 10000390: f000 f967 bl 10000662 10000394: 4603 mov r3, r0 10000396: 2b00 cmp r3, #0 10000398: d001 beq.n 1000039e { return HAL_ERROR; 1000039a: 2301 movs r3, #1 1000039c: e00e b.n 100003bc } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 1000039e: 687b ldr r3, [r7, #4] 100003a0: 2b0f cmp r3, #15 100003a2: d80a bhi.n 100003ba { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 100003a4: 2200 movs r2, #0 100003a6: 6879 ldr r1, [r7, #4] 100003a8: f04f 30ff mov.w r0, #4294967295 100003ac: f000 f92f bl 1000060e uwTickPrio = TickPriority; 100003b0: 4a06 ldr r2, [pc, #24] @ (100003cc ) 100003b2: 687b ldr r3, [r7, #4] 100003b4: 6013 str r3, [r2, #0] #endif /* CORE_CM4 */ /* Return function status */ return HAL_OK; 100003b6: 2300 movs r3, #0 100003b8: e000 b.n 100003bc return HAL_ERROR; 100003ba: 2301 movs r3, #1 } 100003bc: 4618 mov r0, r3 100003be: 3708 adds r7, #8 100003c0: 46bd mov sp, r7 100003c2: bd80 pop {r7, pc} 100003c4: 10020008 .word 0x10020008 100003c8: 10020000 .word 0x10020000 100003cc: 10020004 .word 0x10020004 100003d0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 100003d0: b480 push {r7} 100003d2: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 100003d4: 4b06 ldr r3, [pc, #24] @ (100003f0 ) 100003d6: 781b ldrb r3, [r3, #0] 100003d8: 461a mov r2, r3 100003da: 4b06 ldr r3, [pc, #24] @ (100003f4 ) 100003dc: 681b ldr r3, [r3, #0] 100003de: 4413 add r3, r2 100003e0: 4a04 ldr r2, [pc, #16] @ (100003f4 ) 100003e2: 6013 str r3, [r2, #0] } 100003e4: bf00 nop 100003e6: 46bd mov sp, r7 100003e8: f85d 7b04 ldr.w r7, [sp], #4 100003ec: 4770 bx lr 100003ee: bf00 nop 100003f0: 10020008 .word 0x10020008 100003f4: 10020028 .word 0x10020028 100003f8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 100003f8: b480 push {r7} 100003fa: af00 add r7, sp, #0 #endif /* CORE_CA7 */ #if defined (CORE_CM4) /* tick is incremented in systick handler */ return uwTick; 100003fc: 4b03 ldr r3, [pc, #12] @ (1000040c ) 100003fe: 681b ldr r3, [r3, #0] #endif /* CORE_CM4 */ } 10000400: 4618 mov r0, r3 10000402: 46bd mov sp, r7 10000404: f85d 7b04 ldr.w r7, [sp], #4 10000408: 4770 bx lr 1000040a: bf00 nop 1000040c: 10020028 .word 0x10020028 10000410 : * implementations in user file. * @param Delay: specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 10000410: b580 push {r7, lr} 10000412: b084 sub sp, #16 10000414: af00 add r7, sp, #0 10000416: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 10000418: f7ff ffee bl 100003f8 1000041c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 1000041e: 687b ldr r3, [r7, #4] 10000420: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 10000422: 68fb ldr r3, [r7, #12] 10000424: f1b3 3fff cmp.w r3, #4294967295 10000428: d005 beq.n 10000436 { wait += (uint32_t)(uwTickFreq); 1000042a: 4b0a ldr r3, [pc, #40] @ (10000454 ) 1000042c: 781b ldrb r3, [r3, #0] 1000042e: 461a mov r2, r3 10000430: 68fb ldr r3, [r7, #12] 10000432: 4413 add r3, r2 10000434: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 10000436: bf00 nop 10000438: f7ff ffde bl 100003f8 1000043c: 4602 mov r2, r0 1000043e: 68bb ldr r3, [r7, #8] 10000440: 1ad3 subs r3, r2, r3 10000442: 68fa ldr r2, [r7, #12] 10000444: 429a cmp r2, r3 10000446: d8f7 bhi.n 10000438 { } } 10000448: bf00 nop 1000044a: bf00 nop 1000044c: 3710 adds r7, #16 1000044e: 46bd mov sp, r7 10000450: bd80 pop {r7, pc} 10000452: bf00 nop 10000454: 10020008 .word 0x10020008 10000458 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 10000458: b480 push {r7} 1000045a: b085 sub sp, #20 1000045c: af00 add r7, sp, #0 1000045e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 10000460: 687b ldr r3, [r7, #4] 10000462: f003 0307 and.w r3, r3, #7 10000466: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 10000468: 4b0c ldr r3, [pc, #48] @ (1000049c <__NVIC_SetPriorityGrouping+0x44>) 1000046a: 68db ldr r3, [r3, #12] 1000046c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1000046e: 68ba ldr r2, [r7, #8] 10000470: f64f 03ff movw r3, #63743 @ 0xf8ff 10000474: 4013 ands r3, r2 10000476: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 10000478: 68fb ldr r3, [r7, #12] 1000047a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1000047c: 68bb ldr r3, [r7, #8] 1000047e: 4313 orrs r3, r2 reg_value = (reg_value | 10000480: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 10000484: f443 3300 orr.w r3, r3, #131072 @ 0x20000 10000488: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 1000048a: 4a04 ldr r2, [pc, #16] @ (1000049c <__NVIC_SetPriorityGrouping+0x44>) 1000048c: 68bb ldr r3, [r7, #8] 1000048e: 60d3 str r3, [r2, #12] } 10000490: bf00 nop 10000492: 3714 adds r7, #20 10000494: 46bd mov sp, r7 10000496: f85d 7b04 ldr.w r7, [sp], #4 1000049a: 4770 bx lr 1000049c: e000ed00 .word 0xe000ed00 100004a0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 100004a0: b480 push {r7} 100004a2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 100004a4: 4b04 ldr r3, [pc, #16] @ (100004b8 <__NVIC_GetPriorityGrouping+0x18>) 100004a6: 68db ldr r3, [r3, #12] 100004a8: 0a1b lsrs r3, r3, #8 100004aa: f003 0307 and.w r3, r3, #7 } 100004ae: 4618 mov r0, r3 100004b0: 46bd mov sp, r7 100004b2: f85d 7b04 ldr.w r7, [sp], #4 100004b6: 4770 bx lr 100004b8: e000ed00 .word 0xe000ed00 100004bc <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 100004bc: b480 push {r7} 100004be: b083 sub sp, #12 100004c0: af00 add r7, sp, #0 100004c2: 4603 mov r3, r0 100004c4: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 100004c6: f9b7 3006 ldrsh.w r3, [r7, #6] 100004ca: 2b00 cmp r3, #0 100004cc: db0b blt.n 100004e6 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 100004ce: 88fb ldrh r3, [r7, #6] 100004d0: f003 021f and.w r2, r3, #31 100004d4: 4907 ldr r1, [pc, #28] @ (100004f4 <__NVIC_EnableIRQ+0x38>) 100004d6: f9b7 3006 ldrsh.w r3, [r7, #6] 100004da: 095b lsrs r3, r3, #5 100004dc: 2001 movs r0, #1 100004de: fa00 f202 lsl.w r2, r0, r2 100004e2: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 100004e6: bf00 nop 100004e8: 370c adds r7, #12 100004ea: 46bd mov sp, r7 100004ec: f85d 7b04 ldr.w r7, [sp], #4 100004f0: 4770 bx lr 100004f2: bf00 nop 100004f4: e000e100 .word 0xe000e100 100004f8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 100004f8: b480 push {r7} 100004fa: b083 sub sp, #12 100004fc: af00 add r7, sp, #0 100004fe: 4603 mov r3, r0 10000500: 6039 str r1, [r7, #0] 10000502: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 10000504: f9b7 3006 ldrsh.w r3, [r7, #6] 10000508: 2b00 cmp r3, #0 1000050a: db0a blt.n 10000522 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 1000050c: 683b ldr r3, [r7, #0] 1000050e: b2da uxtb r2, r3 10000510: 490c ldr r1, [pc, #48] @ (10000544 <__NVIC_SetPriority+0x4c>) 10000512: f9b7 3006 ldrsh.w r3, [r7, #6] 10000516: 0112 lsls r2, r2, #4 10000518: b2d2 uxtb r2, r2 1000051a: 440b add r3, r1 1000051c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 10000520: e00a b.n 10000538 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 10000522: 683b ldr r3, [r7, #0] 10000524: b2da uxtb r2, r3 10000526: 4908 ldr r1, [pc, #32] @ (10000548 <__NVIC_SetPriority+0x50>) 10000528: 88fb ldrh r3, [r7, #6] 1000052a: f003 030f and.w r3, r3, #15 1000052e: 3b04 subs r3, #4 10000530: 0112 lsls r2, r2, #4 10000532: b2d2 uxtb r2, r2 10000534: 440b add r3, r1 10000536: 761a strb r2, [r3, #24] } 10000538: bf00 nop 1000053a: 370c adds r7, #12 1000053c: 46bd mov sp, r7 1000053e: f85d 7b04 ldr.w r7, [sp], #4 10000542: 4770 bx lr 10000544: e000e100 .word 0xe000e100 10000548: e000ed00 .word 0xe000ed00 1000054c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 1000054c: b480 push {r7} 1000054e: b089 sub sp, #36 @ 0x24 10000550: af00 add r7, sp, #0 10000552: 60f8 str r0, [r7, #12] 10000554: 60b9 str r1, [r7, #8] 10000556: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 10000558: 68fb ldr r3, [r7, #12] 1000055a: f003 0307 and.w r3, r3, #7 1000055e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 10000560: 69fb ldr r3, [r7, #28] 10000562: f1c3 0307 rsb r3, r3, #7 10000566: 2b04 cmp r3, #4 10000568: bf28 it cs 1000056a: 2304 movcs r3, #4 1000056c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1000056e: 69fb ldr r3, [r7, #28] 10000570: 3304 adds r3, #4 10000572: 2b06 cmp r3, #6 10000574: d902 bls.n 1000057c 10000576: 69fb ldr r3, [r7, #28] 10000578: 3b03 subs r3, #3 1000057a: e000 b.n 1000057e 1000057c: 2300 movs r3, #0 1000057e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 10000580: f04f 32ff mov.w r2, #4294967295 10000584: 69bb ldr r3, [r7, #24] 10000586: fa02 f303 lsl.w r3, r2, r3 1000058a: 43da mvns r2, r3 1000058c: 68bb ldr r3, [r7, #8] 1000058e: 401a ands r2, r3 10000590: 697b ldr r3, [r7, #20] 10000592: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 10000594: f04f 31ff mov.w r1, #4294967295 10000598: 697b ldr r3, [r7, #20] 1000059a: fa01 f303 lsl.w r3, r1, r3 1000059e: 43d9 mvns r1, r3 100005a0: 687b ldr r3, [r7, #4] 100005a2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 100005a4: 4313 orrs r3, r2 ); } 100005a6: 4618 mov r0, r3 100005a8: 3724 adds r7, #36 @ 0x24 100005aa: 46bd mov sp, r7 100005ac: f85d 7b04 ldr.w r7, [sp], #4 100005b0: 4770 bx lr ... 100005b4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 100005b4: b580 push {r7, lr} 100005b6: b082 sub sp, #8 100005b8: af00 add r7, sp, #0 100005ba: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 100005bc: 687b ldr r3, [r7, #4] 100005be: 3b01 subs r3, #1 100005c0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 100005c4: d301 bcc.n 100005ca { return (1UL); /* Reload value impossible */ 100005c6: 2301 movs r3, #1 100005c8: e00f b.n 100005ea } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 100005ca: 4a0a ldr r2, [pc, #40] @ (100005f4 ) 100005cc: 687b ldr r3, [r7, #4] 100005ce: 3b01 subs r3, #1 100005d0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 100005d2: 210f movs r1, #15 100005d4: f04f 30ff mov.w r0, #4294967295 100005d8: f7ff ff8e bl 100004f8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 100005dc: 4b05 ldr r3, [pc, #20] @ (100005f4 ) 100005de: 2200 movs r2, #0 100005e0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 100005e2: 4b04 ldr r3, [pc, #16] @ (100005f4 ) 100005e4: 2207 movs r2, #7 100005e6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 100005e8: 2300 movs r3, #0 } 100005ea: 4618 mov r0, r3 100005ec: 3708 adds r7, #8 100005ee: 46bd mov sp, r7 100005f0: bd80 pop {r7, pc} 100005f2: bf00 nop 100005f4: e000e010 .word 0xe000e010 100005f8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 100005f8: b580 push {r7, lr} 100005fa: b082 sub sp, #8 100005fc: af00 add r7, sp, #0 100005fe: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 10000600: 6878 ldr r0, [r7, #4] 10000602: f7ff ff29 bl 10000458 <__NVIC_SetPriorityGrouping> } 10000606: bf00 nop 10000608: 3708 adds r7, #8 1000060a: 46bd mov sp, r7 1000060c: bd80 pop {r7, pc} 1000060e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 1000060e: b580 push {r7, lr} 10000610: b086 sub sp, #24 10000612: af00 add r7, sp, #0 10000614: 4603 mov r3, r0 10000616: 60b9 str r1, [r7, #8] 10000618: 607a str r2, [r7, #4] 1000061a: 81fb strh r3, [r7, #14] uint32_t prioritygroup = 0x00; 1000061c: 2300 movs r3, #0 1000061e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 10000620: f7ff ff3e bl 100004a0 <__NVIC_GetPriorityGrouping> 10000624: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 10000626: 687a ldr r2, [r7, #4] 10000628: 68b9 ldr r1, [r7, #8] 1000062a: 6978 ldr r0, [r7, #20] 1000062c: f7ff ff8e bl 1000054c 10000630: 4602 mov r2, r0 10000632: f9b7 300e ldrsh.w r3, [r7, #14] 10000636: 4611 mov r1, r2 10000638: 4618 mov r0, r3 1000063a: f7ff ff5d bl 100004f8 <__NVIC_SetPriority> } 1000063e: bf00 nop 10000640: 3718 adds r7, #24 10000642: 46bd mov sp, r7 10000644: bd80 pop {r7, pc} 10000646 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 10000646: b580 push {r7, lr} 10000648: b082 sub sp, #8 1000064a: af00 add r7, sp, #0 1000064c: 4603 mov r3, r0 1000064e: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 10000650: f9b7 3006 ldrsh.w r3, [r7, #6] 10000654: 4618 mov r0, r3 10000656: f7ff ff31 bl 100004bc <__NVIC_EnableIRQ> } 1000065a: bf00 nop 1000065c: 3708 adds r7, #8 1000065e: 46bd mov sp, r7 10000660: bd80 pop {r7, pc} 10000662 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 10000662: b580 push {r7, lr} 10000664: b082 sub sp, #8 10000666: af00 add r7, sp, #0 10000668: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 1000066a: 6878 ldr r0, [r7, #4] 1000066c: f7ff ffa2 bl 100005b4 10000670: 4603 mov r3, r0 } 10000672: 4618 mov r0, r3 10000674: 3708 adds r7, #8 10000676: 46bd mov sp, r7 10000678: bd80 pop {r7, pc} ... 1000067c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 1000067c: b480 push {r7} 1000067e: b089 sub sp, #36 @ 0x24 10000680: af00 add r7, sp, #0 10000682: 6078 str r0, [r7, #4] 10000684: 6039 str r1, [r7, #0] uint32_t iocurrent; uint32_t temp; EXTI_Core_TypeDef * EXTI_CurrentCPU; #if defined(CORE_CM4) EXTI_CurrentCPU = EXTI_C2; /* EXTI for CM4 CPU */ 10000686: 4b8a ldr r3, [pc, #552] @ (100008b0 ) 10000688: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) 1000068a: 2300 movs r3, #0 1000068c: 61fb str r3, [r7, #28] 1000068e: e191 b.n 100009b4 { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; 10000690: 2201 movs r2, #1 10000692: 69fb ldr r3, [r7, #28] 10000694: fa02 f303 lsl.w r3, r2, r3 10000698: 613b str r3, [r7, #16] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 1000069a: 683b ldr r3, [r7, #0] 1000069c: 681b ldr r3, [r3, #0] 1000069e: 693a ldr r2, [r7, #16] 100006a0: 4013 ands r3, r2 100006a2: 60fb str r3, [r7, #12] if(iocurrent == ioposition) 100006a4: 68fa ldr r2, [r7, #12] 100006a6: 693b ldr r3, [r7, #16] 100006a8: 429a cmp r2, r3 100006aa: f040 8180 bne.w 100009ae { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 100006ae: 683b ldr r3, [r7, #0] 100006b0: 685b ldr r3, [r3, #4] 100006b2: 2b02 cmp r3, #2 100006b4: d003 beq.n 100006be 100006b6: 683b ldr r3, [r7, #0] 100006b8: 685b ldr r3, [r3, #4] 100006ba: 2b12 cmp r3, #18 100006bc: d123 bne.n 10000706 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; 100006be: 69fb ldr r3, [r7, #28] 100006c0: 08da lsrs r2, r3, #3 100006c2: 687b ldr r3, [r7, #4] 100006c4: 3208 adds r2, #8 100006c6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 100006ca: 61bb str r3, [r7, #24] temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; 100006cc: 69fb ldr r3, [r7, #28] 100006ce: f003 0307 and.w r3, r3, #7 100006d2: 009b lsls r3, r3, #2 100006d4: 220f movs r2, #15 100006d6: fa02 f303 lsl.w r3, r2, r3 100006da: 43db mvns r3, r3 100006dc: 69ba ldr r2, [r7, #24] 100006de: 4013 ands r3, r2 100006e0: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); 100006e2: 683b ldr r3, [r7, #0] 100006e4: 691a ldr r2, [r3, #16] 100006e6: 69fb ldr r3, [r7, #28] 100006e8: f003 0307 and.w r3, r3, #7 100006ec: 009b lsls r3, r3, #2 100006ee: fa02 f303 lsl.w r3, r2, r3 100006f2: 69ba ldr r2, [r7, #24] 100006f4: 4313 orrs r3, r2 100006f6: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3] = temp; 100006f8: 69fb ldr r3, [r7, #28] 100006fa: 08da lsrs r2, r3, #3 100006fc: 687b ldr r3, [r7, #4] 100006fe: 3208 adds r2, #8 10000700: 69b9 ldr r1, [r7, #24] 10000702: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 10000706: 687b ldr r3, [r7, #4] 10000708: 681b ldr r3, [r3, #0] 1000070a: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2)); 1000070c: 69fb ldr r3, [r7, #28] 1000070e: 005b lsls r3, r3, #1 10000710: 2203 movs r2, #3 10000712: fa02 f303 lsl.w r3, r2, r3 10000716: 43db mvns r3, r3 10000718: 69ba ldr r2, [r7, #24] 1000071a: 4013 ands r3, r2 1000071c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); 1000071e: 683b ldr r3, [r7, #0] 10000720: 685b ldr r3, [r3, #4] 10000722: f003 0203 and.w r2, r3, #3 10000726: 69fb ldr r3, [r7, #28] 10000728: 005b lsls r3, r3, #1 1000072a: fa02 f303 lsl.w r3, r2, r3 1000072e: 69ba ldr r2, [r7, #24] 10000730: 4313 orrs r3, r2 10000732: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 10000734: 687b ldr r3, [r7, #4] 10000736: 69ba ldr r2, [r7, #24] 10000738: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 1000073a: 683b ldr r3, [r7, #0] 1000073c: 685b ldr r3, [r3, #4] 1000073e: 2b01 cmp r3, #1 10000740: d00b beq.n 1000075a 10000742: 683b ldr r3, [r7, #0] 10000744: 685b ldr r3, [r3, #4] 10000746: 2b02 cmp r3, #2 10000748: d007 beq.n 1000075a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 1000074a: 683b ldr r3, [r7, #0] 1000074c: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 1000074e: 2b11 cmp r3, #17 10000750: d003 beq.n 1000075a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 10000752: 683b ldr r3, [r7, #0] 10000754: 685b ldr r3, [r3, #4] 10000756: 2b12 cmp r3, #18 10000758: d130 bne.n 100007bc { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 1000075a: 687b ldr r3, [r7, #4] 1000075c: 689b ldr r3, [r3, #8] 1000075e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2)); 10000760: 69fb ldr r3, [r7, #28] 10000762: 005b lsls r3, r3, #1 10000764: 2203 movs r2, #3 10000766: fa02 f303 lsl.w r3, r2, r3 1000076a: 43db mvns r3, r3 1000076c: 69ba ldr r2, [r7, #24] 1000076e: 4013 ands r3, r2 10000770: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2)); 10000772: 683b ldr r3, [r7, #0] 10000774: 68da ldr r2, [r3, #12] 10000776: 69fb ldr r3, [r7, #28] 10000778: 005b lsls r3, r3, #1 1000077a: fa02 f303 lsl.w r3, r2, r3 1000077e: 69ba ldr r2, [r7, #24] 10000780: 4313 orrs r3, r2 10000782: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 10000784: 687b ldr r3, [r7, #4] 10000786: 69ba ldr r2, [r7, #24] 10000788: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 1000078a: 687b ldr r3, [r7, #4] 1000078c: 685b ldr r3, [r3, #4] 1000078e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 10000790: 2201 movs r2, #1 10000792: 69fb ldr r3, [r7, #28] 10000794: fa02 f303 lsl.w r3, r2, r3 10000798: 43db mvns r3, r3 1000079a: 69ba ldr r2, [r7, #24] 1000079c: 4013 ands r3, r2 1000079e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); 100007a0: 683b ldr r3, [r7, #0] 100007a2: 685b ldr r3, [r3, #4] 100007a4: 091b lsrs r3, r3, #4 100007a6: f003 0201 and.w r2, r3, #1 100007aa: 69fb ldr r3, [r7, #28] 100007ac: fa02 f303 lsl.w r3, r2, r3 100007b0: 69ba ldr r2, [r7, #24] 100007b2: 4313 orrs r3, r2 100007b4: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 100007b6: 687b ldr r3, [r7, #4] 100007b8: 69ba ldr r2, [r7, #24] 100007ba: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 100007bc: 687b ldr r3, [r7, #4] 100007be: 68db ldr r3, [r3, #12] 100007c0: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); 100007c2: 69fb ldr r3, [r7, #28] 100007c4: 005b lsls r3, r3, #1 100007c6: 2203 movs r2, #3 100007c8: fa02 f303 lsl.w r3, r2, r3 100007cc: 43db mvns r3, r3 100007ce: 69ba ldr r2, [r7, #24] 100007d0: 4013 ands r3, r2 100007d2: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2)); 100007d4: 683b ldr r3, [r7, #0] 100007d6: 689a ldr r2, [r3, #8] 100007d8: 69fb ldr r3, [r7, #28] 100007da: 005b lsls r3, r3, #1 100007dc: fa02 f303 lsl.w r3, r2, r3 100007e0: 69ba ldr r2, [r7, #24] 100007e2: 4313 orrs r3, r2 100007e4: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 100007e6: 687b ldr r3, [r7, #4] 100007e8: 69ba ldr r2, [r7, #24] 100007ea: 60da str r2, [r3, #12] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 100007ec: 683b ldr r3, [r7, #0] 100007ee: 685b ldr r3, [r3, #4] 100007f0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 100007f4: 2b00 cmp r3, #0 100007f6: f000 80da beq.w 100009ae { temp = EXTI->EXTICR[position >> 2U]; 100007fa: 4a2e ldr r2, [pc, #184] @ (100008b4 ) 100007fc: 69fb ldr r3, [r7, #28] 100007fe: 089b lsrs r3, r3, #2 10000800: 3318 adds r3, #24 10000802: f852 3023 ldr.w r3, [r2, r3, lsl #2] 10000806: 61bb str r3, [r7, #24] temp &= ~(0xFFU << (8U * (position & 0x03U))); 10000808: 69fb ldr r3, [r7, #28] 1000080a: f003 0303 and.w r3, r3, #3 1000080e: 00db lsls r3, r3, #3 10000810: 22ff movs r2, #255 @ 0xff 10000812: fa02 f303 lsl.w r3, r2, r3 10000816: 43db mvns r3, r3 10000818: 69ba ldr r2, [r7, #24] 1000081a: 4013 ands r3, r2 1000081c: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); 1000081e: 687b ldr r3, [r7, #4] 10000820: 4a25 ldr r2, [pc, #148] @ (100008b8 ) 10000822: 4293 cmp r3, r2 10000824: d05e beq.n 100008e4 10000826: 687b ldr r3, [r7, #4] 10000828: 4a24 ldr r2, [pc, #144] @ (100008bc ) 1000082a: 4293 cmp r3, r2 1000082c: d03d beq.n 100008aa 1000082e: 687b ldr r3, [r7, #4] 10000830: 4a23 ldr r2, [pc, #140] @ (100008c0 ) 10000832: 4293 cmp r3, r2 10000834: d037 beq.n 100008a6 10000836: 687b ldr r3, [r7, #4] 10000838: f1b3 2f50 cmp.w r3, #1342197760 @ 0x50005000 1000083c: d031 beq.n 100008a2 1000083e: 687b ldr r3, [r7, #4] 10000840: 4a20 ldr r2, [pc, #128] @ (100008c4 ) 10000842: 4293 cmp r3, r2 10000844: d02b beq.n 1000089e 10000846: 687b ldr r3, [r7, #4] 10000848: 4a1f ldr r2, [pc, #124] @ (100008c8 ) 1000084a: 4293 cmp r3, r2 1000084c: d025 beq.n 1000089a 1000084e: 687b ldr r3, [r7, #4] 10000850: 4a1e ldr r2, [pc, #120] @ (100008cc ) 10000852: 4293 cmp r3, r2 10000854: d01f beq.n 10000896 10000856: 687b ldr r3, [r7, #4] 10000858: 4a1d ldr r2, [pc, #116] @ (100008d0 ) 1000085a: 4293 cmp r3, r2 1000085c: d019 beq.n 10000892 1000085e: 687b ldr r3, [r7, #4] 10000860: 4a1c ldr r2, [pc, #112] @ (100008d4 ) 10000862: 4293 cmp r3, r2 10000864: d013 beq.n 1000088e 10000866: 687b ldr r3, [r7, #4] 10000868: 4a1b ldr r2, [pc, #108] @ (100008d8 ) 1000086a: 4293 cmp r3, r2 1000086c: d00d beq.n 1000088a 1000086e: 687b ldr r3, [r7, #4] 10000870: 4a1a ldr r2, [pc, #104] @ (100008dc ) 10000872: 4293 cmp r3, r2 10000874: d007 beq.n 10000886 10000876: 687b ldr r3, [r7, #4] 10000878: 4a19 ldr r2, [pc, #100] @ (100008e0 ) 1000087a: 4293 cmp r3, r2 1000087c: d101 bne.n 10000882 1000087e: 230b movs r3, #11 10000880: e031 b.n 100008e6 10000882: 2319 movs r3, #25 10000884: e02f b.n 100008e6 10000886: 230a movs r3, #10 10000888: e02d b.n 100008e6 1000088a: 2309 movs r3, #9 1000088c: e02b b.n 100008e6 1000088e: 2308 movs r3, #8 10000890: e029 b.n 100008e6 10000892: 2307 movs r3, #7 10000894: e027 b.n 100008e6 10000896: 2306 movs r3, #6 10000898: e025 b.n 100008e6 1000089a: 2305 movs r3, #5 1000089c: e023 b.n 100008e6 1000089e: 2304 movs r3, #4 100008a0: e021 b.n 100008e6 100008a2: 2303 movs r3, #3 100008a4: e01f b.n 100008e6 100008a6: 2302 movs r3, #2 100008a8: e01d b.n 100008e6 100008aa: 2301 movs r3, #1 100008ac: e01b b.n 100008e6 100008ae: bf00 nop 100008b0: 5000d0c0 .word 0x5000d0c0 100008b4: 5000d000 .word 0x5000d000 100008b8: 50002000 .word 0x50002000 100008bc: 50003000 .word 0x50003000 100008c0: 50004000 .word 0x50004000 100008c4: 50006000 .word 0x50006000 100008c8: 50007000 .word 0x50007000 100008cc: 50008000 .word 0x50008000 100008d0: 50009000 .word 0x50009000 100008d4: 5000a000 .word 0x5000a000 100008d8: 5000b000 .word 0x5000b000 100008dc: 5000c000 .word 0x5000c000 100008e0: 54004000 .word 0x54004000 100008e4: 2300 movs r3, #0 100008e6: 69fa ldr r2, [r7, #28] 100008e8: f002 0203 and.w r2, r2, #3 100008ec: 00d2 lsls r2, r2, #3 100008ee: 4093 lsls r3, r2 100008f0: 461a mov r2, r3 100008f2: 69bb ldr r3, [r7, #24] 100008f4: 4313 orrs r3, r2 100008f6: 61bb str r3, [r7, #24] EXTI->EXTICR[position >> 2U] = temp; 100008f8: 4934 ldr r1, [pc, #208] @ (100009cc ) 100008fa: 69fb ldr r3, [r7, #28] 100008fc: 089b lsrs r3, r3, #2 100008fe: 3318 adds r3, #24 10000900: 69ba ldr r2, [r7, #24] 10000902: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 10000906: 697b ldr r3, [r7, #20] 10000908: 681b ldr r3, [r3, #0] 1000090a: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 1000090c: 68fb ldr r3, [r7, #12] 1000090e: 43db mvns r3, r3 10000910: 69ba ldr r2, [r7, #24] 10000912: 4013 ands r3, r2 10000914: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 10000916: 683b ldr r3, [r7, #0] 10000918: 685b ldr r3, [r3, #4] 1000091a: f403 3380 and.w r3, r3, #65536 @ 0x10000 1000091e: 2b00 cmp r3, #0 10000920: d003 beq.n 1000092a { temp |= iocurrent; 10000922: 69ba ldr r2, [r7, #24] 10000924: 68fb ldr r3, [r7, #12] 10000926: 4313 orrs r3, r2 10000928: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 1000092a: 697b ldr r3, [r7, #20] 1000092c: 69ba ldr r2, [r7, #24] 1000092e: 601a str r2, [r3, #0] temp = EXTI_CurrentCPU->EMR1; 10000930: 697b ldr r3, [r7, #20] 10000932: 685b ldr r3, [r3, #4] 10000934: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 10000936: 68fb ldr r3, [r7, #12] 10000938: 43db mvns r3, r3 1000093a: 69ba ldr r2, [r7, #24] 1000093c: 4013 ands r3, r2 1000093e: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 10000940: 683b ldr r3, [r7, #0] 10000942: 685b ldr r3, [r3, #4] 10000944: f403 3300 and.w r3, r3, #131072 @ 0x20000 10000948: 2b00 cmp r3, #0 1000094a: d003 beq.n 10000954 { temp |= iocurrent; 1000094c: 69ba ldr r2, [r7, #24] 1000094e: 68fb ldr r3, [r7, #12] 10000950: 4313 orrs r3, r2 10000952: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 10000954: 697b ldr r3, [r7, #20] 10000956: 69ba ldr r2, [r7, #24] 10000958: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 1000095a: 4b1c ldr r3, [pc, #112] @ (100009cc ) 1000095c: 681b ldr r3, [r3, #0] 1000095e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 10000960: 68fb ldr r3, [r7, #12] 10000962: 43db mvns r3, r3 10000964: 69ba ldr r2, [r7, #24] 10000966: 4013 ands r3, r2 10000968: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 1000096a: 683b ldr r3, [r7, #0] 1000096c: 685b ldr r3, [r3, #4] 1000096e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 10000972: 2b00 cmp r3, #0 10000974: d003 beq.n 1000097e { temp |= iocurrent; 10000976: 69ba ldr r2, [r7, #24] 10000978: 68fb ldr r3, [r7, #12] 1000097a: 4313 orrs r3, r2 1000097c: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 1000097e: 4a13 ldr r2, [pc, #76] @ (100009cc ) 10000980: 69bb ldr r3, [r7, #24] 10000982: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 10000984: 4b11 ldr r3, [pc, #68] @ (100009cc ) 10000986: 685b ldr r3, [r3, #4] 10000988: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 1000098a: 68fb ldr r3, [r7, #12] 1000098c: 43db mvns r3, r3 1000098e: 69ba ldr r2, [r7, #24] 10000990: 4013 ands r3, r2 10000992: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 10000994: 683b ldr r3, [r7, #0] 10000996: 685b ldr r3, [r3, #4] 10000998: f403 1300 and.w r3, r3, #2097152 @ 0x200000 1000099c: 2b00 cmp r3, #0 1000099e: d003 beq.n 100009a8 { temp |= iocurrent; 100009a0: 69ba ldr r2, [r7, #24] 100009a2: 68fb ldr r3, [r7, #12] 100009a4: 4313 orrs r3, r2 100009a6: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 100009a8: 4a08 ldr r2, [pc, #32] @ (100009cc ) 100009aa: 69bb ldr r3, [r7, #24] 100009ac: 6053 str r3, [r2, #4] for(position = 0; position < GPIO_NUMBER; position++) 100009ae: 69fb ldr r3, [r7, #28] 100009b0: 3301 adds r3, #1 100009b2: 61fb str r3, [r7, #28] 100009b4: 69fb ldr r3, [r7, #28] 100009b6: 2b0f cmp r3, #15 100009b8: f67f ae6a bls.w 10000690 } } } } 100009bc: bf00 nop 100009be: bf00 nop 100009c0: 3724 adds r7, #36 @ 0x24 100009c2: 46bd mov sp, r7 100009c4: f85d 7b04 ldr.w r7, [sp], #4 100009c8: 4770 bx lr 100009ca: bf00 nop 100009cc: 5000d000 .word 0x5000d000 100009d0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 100009d0: b480 push {r7} 100009d2: b083 sub sp, #12 100009d4: af00 add r7, sp, #0 100009d6: 6078 str r0, [r7, #4] 100009d8: 460b mov r3, r1 100009da: 807b strh r3, [r7, #2] 100009dc: 4613 mov r3, r2 100009de: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 100009e0: 787b ldrb r3, [r7, #1] 100009e2: 2b00 cmp r3, #0 100009e4: d003 beq.n 100009ee { GPIOx->BSRR = GPIO_Pin; 100009e6: 887a ldrh r2, [r7, #2] 100009e8: 687b ldr r3, [r7, #4] 100009ea: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 100009ec: e003 b.n 100009f6 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 100009ee: 887b ldrh r3, [r7, #2] 100009f0: 041a lsls r2, r3, #16 100009f2: 687b ldr r3, [r7, #4] 100009f4: 619a str r2, [r3, #24] } 100009f6: bf00 nop 100009f8: 370c adds r7, #12 100009fa: 46bd mov sp, r7 100009fc: f85d 7b04 ldr.w r7, [sp], #4 10000a00: 4770 bx lr ... 10000a04 : * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 10000a04: b580 push {r7, lr} 10000a06: b084 sub sp, #16 10000a08: af00 add r7, sp, #0 10000a0a: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef result = HAL_OK; 10000a0c: 2300 movs r3, #0 10000a0e: 73fb strb r3, [r7, #15] /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 10000a10: 687b ldr r3, [r7, #4] 10000a12: 2b00 cmp r3, #0 10000a14: d101 bne.n 10000a1a { return HAL_ERROR; 10000a16: 2301 movs r3, #1 10000a18: e320 b.n 1000105c } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 10000a1a: 687b ldr r3, [r7, #4] 10000a1c: 681b ldr r3, [r3, #0] 10000a1e: f003 0301 and.w r3, r3, #1 10000a22: 2b00 cmp r3, #0 10000a24: f000 8081 beq.w 10000b2a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used somewhere in the system it will not be disabled */ if (IS_HSE_IN_USE()) 10000a28: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a2c: 6a1b ldr r3, [r3, #32] 10000a2e: f003 0303 and.w r3, r3, #3 10000a32: 2b01 cmp r3, #1 10000a34: d107 bne.n 10000a46 10000a36: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a3a: 6a1b ldr r3, [r3, #32] 10000a3c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000a40: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000a44: d054 beq.n 10000af0 10000a46: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a4a: 6a5b ldr r3, [r3, #36] @ 0x24 10000a4c: f003 0307 and.w r3, r3, #7 10000a50: 2b01 cmp r3, #1 10000a52: d107 bne.n 10000a64 10000a54: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a58: 6a5b ldr r3, [r3, #36] @ 0x24 10000a5a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000a5e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000a62: d045 beq.n 10000af0 10000a64: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a68: 6c9b ldr r3, [r3, #72] @ 0x48 10000a6a: f003 0303 and.w r3, r3, #3 10000a6e: 2b01 cmp r3, #1 10000a70: d107 bne.n 10000a82 10000a72: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a76: 6c9b ldr r3, [r3, #72] @ 0x48 10000a78: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000a7c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000a80: d036 beq.n 10000af0 10000a82: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a86: 6a9b ldr r3, [r3, #40] @ 0x28 10000a88: f003 0303 and.w r3, r3, #3 10000a8c: 2b01 cmp r3, #1 10000a8e: d10f bne.n 10000ab0 10000a90: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000a94: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 10000a98: f003 0302 and.w r3, r3, #2 10000a9c: 2b02 cmp r3, #2 10000a9e: d027 beq.n 10000af0 10000aa0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000aa4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10000aa8: f003 0302 and.w r3, r3, #2 10000aac: 2b02 cmp r3, #2 10000aae: d01f beq.n 10000af0 10000ab0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ab4: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 10000ab8: f003 0303 and.w r3, r3, #3 10000abc: 2b01 cmp r3, #1 10000abe: d107 bne.n 10000ad0 10000ac0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ac4: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10000ac8: f003 0302 and.w r3, r3, #2 10000acc: 2b02 cmp r3, #2 10000ace: d00f beq.n 10000af0 10000ad0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ad4: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10000ad8: f003 0303 and.w r3, r3, #3 10000adc: 2b01 cmp r3, #1 10000ade: d117 bne.n 10000b10 10000ae0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ae4: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10000ae8: f003 0302 and.w r3, r3, #2 10000aec: 2b02 cmp r3, #2 10000aee: d10f bne.n 10000b10 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) 10000af0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000af4: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000af8: f403 7380 and.w r3, r3, #256 @ 0x100 10000afc: f5b3 7f80 cmp.w r3, #256 @ 0x100 10000b00: d112 bne.n 10000b28 10000b02: 687b ldr r3, [r7, #4] 10000b04: 685b ldr r3, [r3, #4] 10000b06: f5b3 7f80 cmp.w r3, #256 @ 0x100 10000b0a: d00d beq.n 10000b28 { return HAL_ERROR; 10000b0c: 2301 movs r3, #1 10000b0e: e2a5 b.n 1000105c } } else { /* Configure HSE oscillator */ result = HAL_RCC_HSEConfig(RCC_OscInitStruct->HSEState); 10000b10: 687b ldr r3, [r7, #4] 10000b12: 685b ldr r3, [r3, #4] 10000b14: 4618 mov r0, r3 10000b16: f000 faa7 bl 10001068 10000b1a: 4603 mov r3, r0 10000b1c: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10000b1e: 7bfb ldrb r3, [r7, #15] 10000b20: 2b00 cmp r3, #0 10000b22: d002 beq.n 10000b2a { return result; 10000b24: 7bfb ldrb r3, [r7, #15] 10000b26: e299 b.n 1000105c if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) 10000b28: bf00 nop } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 10000b2a: 687b ldr r3, [r7, #4] 10000b2c: 681b ldr r3, [r3, #0] 10000b2e: f003 0302 and.w r3, r3, #2 10000b32: 2b00 cmp r3, #0 10000b34: f000 814e beq.w 10000dd4 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDivValue)); /* When the HSI is used as system clock it will not disabled */ if (IS_HSI_IN_USE()) 10000b38: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b3c: 6a1b ldr r3, [r3, #32] 10000b3e: f003 0303 and.w r3, r3, #3 10000b42: 2b00 cmp r3, #0 10000b44: d107 bne.n 10000b56 10000b46: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b4a: 6a1b ldr r3, [r3, #32] 10000b4c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000b50: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000b54: d055 beq.n 10000c02 10000b56: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b5a: 6a5b ldr r3, [r3, #36] @ 0x24 10000b5c: f003 0307 and.w r3, r3, #7 10000b60: 2b00 cmp r3, #0 10000b62: d107 bne.n 10000b74 10000b64: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b68: 6a5b ldr r3, [r3, #36] @ 0x24 10000b6a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000b6e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000b72: d046 beq.n 10000c02 10000b74: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b78: 6c9b ldr r3, [r3, #72] @ 0x48 10000b7a: f003 0303 and.w r3, r3, #3 10000b7e: 2b00 cmp r3, #0 10000b80: d107 bne.n 10000b92 10000b82: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b86: 6c9b ldr r3, [r3, #72] @ 0x48 10000b88: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000b8c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000b90: d037 beq.n 10000c02 10000b92: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000b96: 6a9b ldr r3, [r3, #40] @ 0x28 10000b98: f003 0303 and.w r3, r3, #3 10000b9c: 2b00 cmp r3, #0 10000b9e: d10f bne.n 10000bc0 10000ba0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ba4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 10000ba8: f003 0302 and.w r3, r3, #2 10000bac: 2b02 cmp r3, #2 10000bae: d028 beq.n 10000c02 10000bb0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000bb4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10000bb8: f003 0302 and.w r3, r3, #2 10000bbc: 2b02 cmp r3, #2 10000bbe: d020 beq.n 10000c02 10000bc0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000bc4: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 10000bc8: f003 0303 and.w r3, r3, #3 10000bcc: 2b00 cmp r3, #0 10000bce: d107 bne.n 10000be0 10000bd0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000bd4: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10000bd8: f003 0302 and.w r3, r3, #2 10000bdc: 2b02 cmp r3, #2 10000bde: d010 beq.n 10000c02 10000be0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000be4: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10000be8: f003 0303 and.w r3, r3, #3 10000bec: 2b00 cmp r3, #0 10000bee: f040 8088 bne.w 10000d02 10000bf2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000bf6: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10000bfa: f003 0302 and.w r3, r3, #2 10000bfe: 2b02 cmp r3, #2 10000c00: d17f bne.n 10000d02 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 10000c02: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c06: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000c0a: f003 0301 and.w r3, r3, #1 10000c0e: 2b01 cmp r3, #1 10000c10: d105 bne.n 10000c1e 10000c12: 687b ldr r3, [r7, #4] 10000c14: 68db ldr r3, [r3, #12] 10000c16: 2b01 cmp r3, #1 10000c18: d001 beq.n 10000c1e { return HAL_ERROR; 10000c1a: 2301 movs r3, #1 10000c1c: e21e b.n 1000105c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 10000c1e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c22: 699b ldr r3, [r3, #24] 10000c24: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 10000c28: 687b ldr r3, [r7, #4] 10000c2a: 691b ldr r3, [r3, #16] 10000c2c: 021b lsls r3, r3, #8 10000c2e: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000c32: 4313 orrs r3, r2 10000c34: 618b str r3, [r1, #24] /* It is not allowed to change HSIDIV if HSI is currently used as * reference clock for a PLL */ if (((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) || 10000c36: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c3a: 6a9b ldr r3, [r3, #40] @ 0x28 10000c3c: f003 0303 and.w r3, r3, #3 10000c40: 2b00 cmp r3, #0 10000c42: d10f bne.n 10000c64 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY)) && 10000c44: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c48: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 10000c4c: f003 0302 and.w r3, r3, #2 if (((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) || 10000c50: 2b02 cmp r3, #2 10000c52: d047 beq.n 10000ce4 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY))))) && 10000c54: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c58: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10000c5c: f003 0302 and.w r3, r3, #2 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY)) && 10000c60: 2b02 cmp r3, #2 10000c62: d03f beq.n 10000ce4 ((__HAL_RCC_GET_PLL3_SOURCE() != RCC_PLL3SOURCE_HSI) || 10000c64: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c68: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 10000c6c: f003 0303 and.w r3, r3, #3 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY))))) && 10000c70: 2b00 cmp r3, #0 10000c72: d107 bne.n 10000c84 (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY))) && 10000c74: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c78: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10000c7c: f003 0302 and.w r3, r3, #2 ((__HAL_RCC_GET_PLL3_SOURCE() != RCC_PLL3SOURCE_HSI) || 10000c80: 2b02 cmp r3, #2 10000c82: d02f beq.n 10000ce4 ((__HAL_RCC_GET_PLL4_SOURCE() != RCC_PLL4SOURCE_HSI) || 10000c84: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c88: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10000c8c: f003 0303 and.w r3, r3, #3 (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY))) && 10000c90: 2b00 cmp r3, #0 10000c92: d107 bne.n 10000ca4 (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY)))) 10000c94: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000c98: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10000c9c: f003 0302 and.w r3, r3, #2 ((__HAL_RCC_GET_PLL4_SOURCE() != RCC_PLL4SOURCE_HSI) || 10000ca0: 2b02 cmp r3, #2 10000ca2: d01f beq.n 10000ce4 { /* Update HSIDIV value */ __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue); 10000ca4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ca8: 699b ldr r3, [r3, #24] 10000caa: f023 0203 bic.w r2, r3, #3 10000cae: 687b ldr r3, [r7, #4] 10000cb0: 695b ldr r3, [r3, #20] 10000cb2: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000cb6: 4313 orrs r3, r2 10000cb8: 618b str r3, [r1, #24] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000cba: f7ff fb9d bl 100003f8 10000cbe: 60b8 str r0, [r7, #8] /* Wait till HSIDIV is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET) 10000cc0: e008 b.n 10000cd4 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 10000cc2: f7ff fb99 bl 100003f8 10000cc6: 4602 mov r2, r0 10000cc8: 68bb ldr r3, [r7, #8] 10000cca: 1ad3 subs r3, r2, r3 10000ccc: 2b64 cmp r3, #100 @ 0x64 10000cce: d901 bls.n 10000cd4 { return HAL_TIMEOUT; 10000cd0: 2303 movs r3, #3 10000cd2: e1c3 b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET) 10000cd4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000cd8: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000cdc: f003 0304 and.w r3, r3, #4 10000ce0: 2b04 cmp r3, #4 10000ce2: d1ee bne.n 10000cc2 } } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); 10000ce4: f001 f809 bl 10001cfa 10000ce8: 4603 mov r3, r0 10000cea: 4ab3 ldr r2, [pc, #716] @ (10000fb8 ) 10000cec: 6013 str r3, [r2, #0] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 10000cee: 4bb3 ldr r3, [pc, #716] @ (10000fbc ) 10000cf0: 681b ldr r3, [r3, #0] 10000cf2: 4618 mov r0, r3 10000cf4: f7ff fb36 bl 10000364 10000cf8: 4603 mov r3, r0 10000cfa: 2b00 cmp r3, #0 10000cfc: d069 beq.n 10000dd2 { return HAL_ERROR; 10000cfe: 2301 movs r3, #1 10000d00: e1ac b.n 1000105c } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 10000d02: 687b ldr r3, [r7, #4] 10000d04: 68db ldr r3, [r3, #12] 10000d06: 2b00 cmp r3, #0 10000d08: d049 beq.n 10000d9e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 10000d0a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000d0e: 68db ldr r3, [r3, #12] 10000d10: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10000d14: f043 0301 orr.w r3, r3, #1 10000d18: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000d1a: f7ff fb6d bl 100003f8 10000d1e: 60b8 str r0, [r7, #8] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 10000d20: e008 b.n 10000d34 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 10000d22: f7ff fb69 bl 100003f8 10000d26: 4602 mov r2, r0 10000d28: 68bb ldr r3, [r7, #8] 10000d2a: 1ad3 subs r3, r2, r3 10000d2c: 2b64 cmp r3, #100 @ 0x64 10000d2e: d901 bls.n 10000d34 { return HAL_TIMEOUT; 10000d30: 2303 movs r3, #3 10000d32: e193 b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 10000d34: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000d38: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000d3c: f003 0301 and.w r3, r3, #1 10000d40: 2b01 cmp r3, #1 10000d42: d1ee bne.n 10000d22 } } /* Update HSIDIV value */ __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue); 10000d44: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000d48: 699b ldr r3, [r3, #24] 10000d4a: f023 0203 bic.w r2, r3, #3 10000d4e: 687b ldr r3, [r7, #4] 10000d50: 695b ldr r3, [r3, #20] 10000d52: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000d56: 4313 orrs r3, r2 10000d58: 618b str r3, [r1, #24] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000d5a: f7ff fb4d bl 100003f8 10000d5e: 60b8 str r0, [r7, #8] /* Wait till HSIDIV is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET) 10000d60: e008 b.n 10000d74 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 10000d62: f7ff fb49 bl 100003f8 10000d66: 4602 mov r2, r0 10000d68: 68bb ldr r3, [r7, #8] 10000d6a: 1ad3 subs r3, r2, r3 10000d6c: 2b64 cmp r3, #100 @ 0x64 10000d6e: d901 bls.n 10000d74 { return HAL_TIMEOUT; 10000d70: 2303 movs r3, #3 10000d72: e173 b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET) 10000d74: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000d78: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000d7c: f003 0304 and.w r3, r3, #4 10000d80: 2b04 cmp r3, #4 10000d82: d1ee bne.n 10000d62 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 10000d84: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000d88: 699b ldr r3, [r3, #24] 10000d8a: f423 42fe bic.w r2, r3, #32512 @ 0x7f00 10000d8e: 687b ldr r3, [r7, #4] 10000d90: 691b ldr r3, [r3, #16] 10000d92: 021b lsls r3, r3, #8 10000d94: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000d98: 4313 orrs r3, r2 10000d9a: 618b str r3, [r1, #24] 10000d9c: e01a b.n 10000dd4 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 10000d9e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000da2: 2201 movs r2, #1 10000da4: 611a str r2, [r3, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000da6: f7ff fb27 bl 100003f8 10000daa: 60b8 str r0, [r7, #8] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 10000dac: e008 b.n 10000dc0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 10000dae: f7ff fb23 bl 100003f8 10000db2: 4602 mov r2, r0 10000db4: 68bb ldr r3, [r7, #8] 10000db6: 1ad3 subs r3, r2, r3 10000db8: 2b64 cmp r3, #100 @ 0x64 10000dba: d901 bls.n 10000dc0 { return HAL_TIMEOUT; 10000dbc: 2303 movs r3, #3 10000dbe: e14d b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 10000dc0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000dc4: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000dc8: f003 0301 and.w r3, r3, #1 10000dcc: 2b01 cmp r3, #1 10000dce: d0ee beq.n 10000dae 10000dd0: e000 b.n 10000dd4 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 10000dd2: bf00 nop } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 10000dd4: 687b ldr r3, [r7, #4] 10000dd6: 681b ldr r3, [r3, #0] 10000dd8: f003 0310 and.w r3, r3, #16 10000ddc: 2b00 cmp r3, #0 10000dde: f000 8091 beq.w 10000f04 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ if (IS_CSI_IN_USE()) 10000de2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000de6: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 10000dea: f003 0303 and.w r3, r3, #3 10000dee: 2b02 cmp r3, #2 10000df0: d107 bne.n 10000e02 10000df2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000df6: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10000dfa: f003 0302 and.w r3, r3, #2 10000dfe: 2b02 cmp r3, #2 10000e00: d01e beq.n 10000e40 10000e02: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e06: 6c9b ldr r3, [r3, #72] @ 0x48 10000e08: f003 0303 and.w r3, r3, #3 10000e0c: 2b02 cmp r3, #2 10000e0e: d107 bne.n 10000e20 10000e10: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e14: 6c9b ldr r3, [r3, #72] @ 0x48 10000e16: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10000e1a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10000e1e: d00f beq.n 10000e40 10000e20: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e24: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10000e28: f003 0303 and.w r3, r3, #3 10000e2c: 2b02 cmp r3, #2 10000e2e: d122 bne.n 10000e76 10000e30: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e34: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10000e38: f003 0302 and.w r3, r3, #2 10000e3c: 2b02 cmp r3, #2 10000e3e: d11a bne.n 10000e76 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 10000e40: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e44: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000e48: f003 0310 and.w r3, r3, #16 10000e4c: 2b10 cmp r3, #16 10000e4e: d105 bne.n 10000e5c 10000e50: 687b ldr r3, [r7, #4] 10000e52: 69db ldr r3, [r3, #28] 10000e54: 2b10 cmp r3, #16 10000e56: d001 beq.n 10000e5c { return HAL_ERROR; 10000e58: 2301 movs r3, #1 10000e5a: e0ff b.n 1000105c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 10000e5c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e60: 69db ldr r3, [r3, #28] 10000e62: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 10000e66: 687b ldr r3, [r7, #4] 10000e68: 6a1b ldr r3, [r3, #32] 10000e6a: 021b lsls r3, r3, #8 10000e6c: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000e70: 4313 orrs r3, r2 10000e72: 61cb str r3, [r1, #28] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 10000e74: e046 b.n 10000f04 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 10000e76: 687b ldr r3, [r7, #4] 10000e78: 69db ldr r3, [r3, #28] 10000e7a: 2b00 cmp r3, #0 10000e7c: d029 beq.n 10000ed2 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 10000e7e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000e82: 68db ldr r3, [r3, #12] 10000e84: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10000e88: f043 0310 orr.w r3, r3, #16 10000e8c: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000e8e: f7ff fab3 bl 100003f8 10000e92: 60b8 str r0, [r7, #8] /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET) 10000e94: e008 b.n 10000ea8 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 10000e96: f7ff faaf bl 100003f8 10000e9a: 4602 mov r2, r0 10000e9c: 68bb ldr r3, [r7, #8] 10000e9e: 1ad3 subs r3, r2, r3 10000ea0: 2b64 cmp r3, #100 @ 0x64 10000ea2: d901 bls.n 10000ea8 { return HAL_TIMEOUT; 10000ea4: 2303 movs r3, #3 10000ea6: e0d9 b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET) 10000ea8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000eac: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000eb0: f003 0310 and.w r3, r3, #16 10000eb4: 2b10 cmp r3, #16 10000eb6: d1ee bne.n 10000e96 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 10000eb8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ebc: 69db ldr r3, [r3, #28] 10000ebe: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 10000ec2: 687b ldr r3, [r7, #4] 10000ec4: 6a1b ldr r3, [r3, #32] 10000ec6: 021b lsls r3, r3, #8 10000ec8: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10000ecc: 4313 orrs r3, r2 10000ece: 61cb str r3, [r1, #28] 10000ed0: e018 b.n 10000f04 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 10000ed2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ed6: 2210 movs r2, #16 10000ed8: 611a str r2, [r3, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000eda: f7ff fa8d bl 100003f8 10000ede: 60b8 str r0, [r7, #8] /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) 10000ee0: e008 b.n 10000ef4 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 10000ee2: f7ff fa89 bl 100003f8 10000ee6: 4602 mov r2, r0 10000ee8: 68bb ldr r3, [r7, #8] 10000eea: 1ad3 subs r3, r2, r3 10000eec: 2b64 cmp r3, #100 @ 0x64 10000eee: d901 bls.n 10000ef4 { return HAL_TIMEOUT; 10000ef0: 2303 movs r3, #3 10000ef2: e0b3 b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) 10000ef4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000ef8: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10000efc: f003 0310 and.w r3, r3, #16 10000f00: 2b10 cmp r3, #16 10000f02: d0ee beq.n 10000ee2 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 10000f04: 687b ldr r3, [r7, #4] 10000f06: 681b ldr r3, [r3, #0] 10000f08: f003 0308 and.w r3, r3, #8 10000f0c: 2b00 cmp r3, #0 10000f0e: d042 beq.n 10000f96 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 10000f10: 687b ldr r3, [r7, #4] 10000f12: 699b ldr r3, [r3, #24] 10000f14: 2b00 cmp r3, #0 10000f16: d01f beq.n 10000f58 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 10000f18: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000f1c: f8d3 3144 ldr.w r3, [r3, #324] @ 0x144 10000f20: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10000f24: f043 0301 orr.w r3, r3, #1 10000f28: f8c2 3144 str.w r3, [r2, #324] @ 0x144 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000f2c: f7ff fa64 bl 100003f8 10000f30: 60b8 str r0, [r7, #8] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 10000f32: e008 b.n 10000f46 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 10000f34: f7ff fa60 bl 100003f8 10000f38: 4602 mov r2, r0 10000f3a: 68bb ldr r3, [r7, #8] 10000f3c: 1ad3 subs r3, r2, r3 10000f3e: 2b64 cmp r3, #100 @ 0x64 10000f40: d901 bls.n 10000f46 { return HAL_TIMEOUT; 10000f42: 2303 movs r3, #3 10000f44: e08a b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 10000f46: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000f4a: f8d3 3144 ldr.w r3, [r3, #324] @ 0x144 10000f4e: f003 0302 and.w r3, r3, #2 10000f52: 2b02 cmp r3, #2 10000f54: d1ee bne.n 10000f34 10000f56: e01e b.n 10000f96 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 10000f58: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000f5c: f8d3 3144 ldr.w r3, [r3, #324] @ 0x144 10000f60: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10000f64: f023 0301 bic.w r3, r3, #1 10000f68: f8c2 3144 str.w r3, [r2, #324] @ 0x144 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10000f6c: f7ff fa44 bl 100003f8 10000f70: 60b8 str r0, [r7, #8] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 10000f72: e008 b.n 10000f86 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 10000f74: f7ff fa40 bl 100003f8 10000f78: 4602 mov r2, r0 10000f7a: 68bb ldr r3, [r7, #8] 10000f7c: 1ad3 subs r3, r2, r3 10000f7e: 2b64 cmp r3, #100 @ 0x64 10000f80: d901 bls.n 10000f86 { return HAL_TIMEOUT; 10000f82: 2303 movs r3, #3 10000f84: e06a b.n 1000105c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 10000f86: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10000f8a: f8d3 3144 ldr.w r3, [r3, #324] @ 0x144 10000f8e: f003 0302 and.w r3, r3, #2 10000f92: 2b02 cmp r3, #2 10000f94: d0ee beq.n 10000f74 } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 10000f96: 687b ldr r3, [r7, #4] 10000f98: 681b ldr r3, [r3, #0] 10000f9a: f003 0304 and.w r3, r3, #4 10000f9e: 2b00 cmp r3, #0 10000fa0: d02b beq.n 10000ffa { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 10000fa2: 4b07 ldr r3, [pc, #28] @ (10000fc0 ) 10000fa4: 681b ldr r3, [r3, #0] 10000fa6: 4a06 ldr r2, [pc, #24] @ (10000fc0 ) 10000fa8: f443 7380 orr.w r3, r3, #256 @ 0x100 10000fac: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 10000fae: f7ff fa23 bl 100003f8 10000fb2: 60b8 str r0, [r7, #8] while ((PWR->CR1 & PWR_CR1_DBP) == RESET) 10000fb4: e00f b.n 10000fd6 10000fb6: bf00 nop 10000fb8: 10020000 .word 0x10020000 10000fbc: 10020004 .word 0x10020004 10000fc0: 50001000 .word 0x50001000 { if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) 10000fc4: f7ff fa18 bl 100003f8 10000fc8: 4602 mov r2, r0 10000fca: 68bb ldr r3, [r7, #8] 10000fcc: 1ad3 subs r3, r2, r3 10000fce: 2b64 cmp r3, #100 @ 0x64 10000fd0: d901 bls.n 10000fd6 { return HAL_TIMEOUT; 10000fd2: 2303 movs r3, #3 10000fd4: e042 b.n 1000105c while ((PWR->CR1 & PWR_CR1_DBP) == RESET) 10000fd6: 4b23 ldr r3, [pc, #140] @ (10001064 ) 10000fd8: 681b ldr r3, [r3, #0] 10000fda: f403 7380 and.w r3, r3, #256 @ 0x100 10000fde: 2b00 cmp r3, #0 10000fe0: d0f0 beq.n 10000fc4 } } result = HAL_RCC_LSEConfig(RCC_OscInitStruct->LSEState); 10000fe2: 687b ldr r3, [r7, #4] 10000fe4: 689b ldr r3, [r3, #8] 10000fe6: 4618 mov r0, r3 10000fe8: f000 f8a9 bl 1000113e 10000fec: 4603 mov r3, r0 10000fee: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10000ff0: 7bfb ldrb r3, [r7, #15] 10000ff2: 2b00 cmp r3, #0 10000ff4: d001 beq.n 10000ffa { return result; 10000ff6: 7bfb ldrb r3, [r7, #15] 10000ff8: e030 b.n 1000105c } /* Close LSE Configuration */ /*-------------------------------- PLL Configuration -----------------------*/ /* Configure PLL1 */ result = RCC_PLL1_Config(&(RCC_OscInitStruct->PLL)); 10000ffa: 687b ldr r3, [r7, #4] 10000ffc: 3324 adds r3, #36 @ 0x24 10000ffe: 4618 mov r0, r3 10001000: f000 f91a bl 10001238 10001004: 4603 mov r3, r0 10001006: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10001008: 7bfb ldrb r3, [r7, #15] 1000100a: 2b00 cmp r3, #0 1000100c: d001 beq.n 10001012 { return result; 1000100e: 7bfb ldrb r3, [r7, #15] 10001010: e024 b.n 1000105c } /* Configure PLL2 */ result = RCCEx_PLL2_Config(&(RCC_OscInitStruct->PLL2)); 10001012: 687b ldr r3, [r7, #4] 10001014: 3360 adds r3, #96 @ 0x60 10001016: 4618 mov r0, r3 10001018: f000 fecc bl 10001db4 1000101c: 4603 mov r3, r0 1000101e: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10001020: 7bfb ldrb r3, [r7, #15] 10001022: 2b00 cmp r3, #0 10001024: d001 beq.n 1000102a { return result; 10001026: 7bfb ldrb r3, [r7, #15] 10001028: e018 b.n 1000105c } /* Configure PLL3 */ result = RCCEx_PLL3_Config(&(RCC_OscInitStruct->PLL3)); 1000102a: 687b ldr r3, [r7, #4] 1000102c: 339c adds r3, #156 @ 0x9c 1000102e: 4618 mov r0, r3 10001030: f001 f842 bl 100020b8 10001034: 4603 mov r3, r0 10001036: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10001038: 7bfb ldrb r3, [r7, #15] 1000103a: 2b00 cmp r3, #0 1000103c: d001 beq.n 10001042 { return result; 1000103e: 7bfb ldrb r3, [r7, #15] 10001040: e00c b.n 1000105c } /* Configure PLL4 */ result = RCCEx_PLL4_Config(&(RCC_OscInitStruct->PLL4)); 10001042: 687b ldr r3, [r7, #4] 10001044: 33d8 adds r3, #216 @ 0xd8 10001046: 4618 mov r0, r3 10001048: f001 f9a0 bl 1000238c 1000104c: 4603 mov r3, r0 1000104e: 73fb strb r3, [r7, #15] if (result != HAL_OK) 10001050: 7bfb ldrb r3, [r7, #15] 10001052: 2b00 cmp r3, #0 10001054: d001 beq.n 1000105a { return result; 10001056: 7bfb ldrb r3, [r7, #15] 10001058: e000 b.n 1000105c } return HAL_OK; 1000105a: 2300 movs r3, #0 } 1000105c: 4618 mov r0, r3 1000105e: 3710 adds r7, #16 10001060: 46bd mov sp, r7 10001062: bd80 pop {r7, pc} 10001064: 50001000 .word 0x50001000 10001068 : * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external * clock using a full-swing digital signal provided to OSC_IN * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State) { 10001068: b580 push {r7, lr} 1000106a: b084 sub sp, #16 1000106c: af00 add r7, sp, #0 1000106e: 6078 str r0, [r7, #4] /* Check parameter */ assert_param(IS_RCC_HSE(State)); /* Disable HSEON before configuring the HSE --------------*/ WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEON); 10001070: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001074: f44f 7280 mov.w r2, #256 @ 0x100 10001078: 611a str r2, [r3, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000107a: f7ff f9bd bl 100003f8 1000107e: 60f8 str r0, [r7, #12] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 10001080: e008 b.n 10001094 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 10001082: f7ff f9b9 bl 100003f8 10001086: 4602 mov r2, r0 10001088: 68fb ldr r3, [r7, #12] 1000108a: 1ad3 subs r3, r2, r3 1000108c: 2b64 cmp r3, #100 @ 0x64 1000108e: d901 bls.n 10001094 { return HAL_TIMEOUT; 10001090: 2303 movs r3, #3 10001092: e050 b.n 10001136 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 10001094: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001098: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 1000109c: f403 7380 and.w r3, r3, #256 @ 0x100 100010a0: f5b3 7f80 cmp.w r3, #256 @ 0x100 100010a4: d0ed beq.n 10001082 } } /* Clear remaining bits */ WRITE_REG(RCC->OCENCLRR, (RCC_OCENCLRR_DIGBYP | RCC_OCENSETR_HSEBYP)); 100010a6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100010aa: f44f 6290 mov.w r2, #1152 @ 0x480 100010ae: 611a str r2, [r3, #16] /* Enable HSE if needed ---------------------------------------*/ if (State != RCC_HSE_OFF) 100010b0: 687b ldr r3, [r7, #4] 100010b2: 2b00 cmp r3, #0 100010b4: d03e beq.n 10001134 { if (State == RCC_HSE_BYPASS) 100010b6: 687b ldr r3, [r7, #4] 100010b8: f5b3 6fa0 cmp.w r3, #1280 @ 0x500 100010bc: d108 bne.n 100010d0 { SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP); 100010be: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100010c2: 68db ldr r3, [r3, #12] 100010c4: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100010c8: f443 6380 orr.w r3, r3, #1024 @ 0x400 100010cc: 60d3 str r3, [r2, #12] 100010ce: e013 b.n 100010f8 } else if (State == RCC_HSE_BYPASS_DIG) 100010d0: 687b ldr r3, [r7, #4] 100010d2: f5b3 6fb0 cmp.w r3, #1408 @ 0x580 100010d6: d10f bne.n 100010f8 { SET_BIT(RCC->OCENSETR, RCC_OCENCLRR_DIGBYP); 100010d8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100010dc: 68db ldr r3, [r3, #12] 100010de: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100010e2: f043 0380 orr.w r3, r3, #128 @ 0x80 100010e6: 60d3 str r3, [r2, #12] SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP); 100010e8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100010ec: 68db ldr r3, [r3, #12] 100010ee: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100010f2: f443 6380 orr.w r3, r3, #1024 @ 0x400 100010f6: 60d3 str r3, [r2, #12] } /* Enable oscillator */ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEON); 100010f8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100010fc: 68db ldr r3, [r3, #12] 100010fe: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001102: f443 7380 orr.w r3, r3, #256 @ 0x100 10001106: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001108: f7ff f976 bl 100003f8 1000110c: 60f8 str r0, [r7, #12] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 1000110e: e008 b.n 10001122 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 10001110: f7ff f972 bl 100003f8 10001114: 4602 mov r2, r0 10001116: 68fb ldr r3, [r7, #12] 10001118: 1ad3 subs r3, r2, r3 1000111a: 2b64 cmp r3, #100 @ 0x64 1000111c: d901 bls.n 10001122 { return HAL_TIMEOUT; 1000111e: 2303 movs r3, #3 10001120: e009 b.n 10001136 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 10001122: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001126: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 1000112a: f403 7380 and.w r3, r3, #256 @ 0x100 1000112e: f5b3 7f80 cmp.w r3, #256 @ 0x100 10001132: d1ed bne.n 10001110 } } } return HAL_OK; 10001134: 2300 movs r3, #0 } 10001136: 4618 mov r0, r3 10001138: 3710 adds r7, #16 1000113a: 46bd mov sp, r7 1000113c: bd80 pop {r7, pc} 1000113e : * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external * clock using a full-swing digital signal provided to OSC32_IN * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State) { 1000113e: b580 push {r7, lr} 10001140: b084 sub sp, #16 10001142: af00 add r7, sp, #0 10001144: 6078 str r0, [r7, #4] /* Check parameter */ assert_param(IS_RCC_LSE(State)); /* Turning LSE off is needed before configuring */ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 10001146: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000114a: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 1000114e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001152: f023 0301 bic.w r3, r3, #1 10001156: f8c2 3140 str.w r3, [r2, #320] @ 0x140 /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000115a: f7ff f94d bl 100003f8 1000115e: 60f8 str r0, [r7, #12] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 10001160: e00a b.n 10001178 { if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) 10001162: f7ff f949 bl 100003f8 10001166: 4602 mov r2, r0 10001168: 68fb ldr r3, [r7, #12] 1000116a: 1ad3 subs r3, r2, r3 1000116c: f241 3288 movw r2, #5000 @ 0x1388 10001170: 4293 cmp r3, r2 10001172: d901 bls.n 10001178 { return HAL_TIMEOUT; 10001174: 2303 movs r3, #3 10001176: e05b b.n 10001230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 10001178: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000117c: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 10001180: f003 0304 and.w r3, r3, #4 10001184: 2b04 cmp r3, #4 10001186: d0ec beq.n 10001162 } } /* Clear remaining bits */ CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)); 10001188: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000118c: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 10001190: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001194: f023 030a bic.w r3, r3, #10 10001198: f8c2 3140 str.w r3, [r2, #320] @ 0x140 /* Enable LSE if needed */ if (State != RCC_LSE_OFF) 1000119c: 687b ldr r3, [r7, #4] 1000119e: 2b00 cmp r3, #0 100011a0: d045 beq.n 1000122e { if (State == RCC_LSE_BYPASS) 100011a2: 687b ldr r3, [r7, #4] 100011a4: 2b03 cmp r3, #3 100011a6: d10a bne.n 100011be { SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 100011a8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100011ac: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 100011b0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100011b4: f043 0302 orr.w r3, r3, #2 100011b8: f8c2 3140 str.w r3, [r2, #320] @ 0x140 100011bc: e016 b.n 100011ec } else if (State == RCC_LSE_BYPASS_DIG) 100011be: 687b ldr r3, [r7, #4] 100011c0: 2b0b cmp r3, #11 100011c2: d113 bne.n 100011ec { SET_BIT(RCC->BDCR, RCC_BDCR_DIGBYP); 100011c4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100011c8: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 100011cc: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100011d0: f043 0308 orr.w r3, r3, #8 100011d4: f8c2 3140 str.w r3, [r2, #320] @ 0x140 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 100011d8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100011dc: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 100011e0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100011e4: f043 0302 orr.w r3, r3, #2 100011e8: f8c2 3140 str.w r3, [r2, #320] @ 0x140 } /* Enable oscillator */ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 100011ec: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100011f0: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 100011f4: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100011f8: f043 0301 orr.w r3, r3, #1 100011fc: f8c2 3140 str.w r3, [r2, #320] @ 0x140 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001200: f7ff f8fa bl 100003f8 10001204: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 10001206: e00a b.n 1000121e { if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) 10001208: f7ff f8f6 bl 100003f8 1000120c: 4602 mov r2, r0 1000120e: 68fb ldr r3, [r7, #12] 10001210: 1ad3 subs r3, r2, r3 10001212: f241 3288 movw r2, #5000 @ 0x1388 10001216: 4293 cmp r3, r2 10001218: d901 bls.n 1000121e { return HAL_TIMEOUT; 1000121a: 2303 movs r3, #3 1000121c: e008 b.n 10001230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 1000121e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001222: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 10001226: f003 0304 and.w r3, r3, #4 1000122a: 2b04 cmp r3, #4 1000122c: d1ec bne.n 10001208 } } } /* Enable LSE if needed */ return HAL_OK; 1000122e: 2300 movs r3, #0 } 10001230: 4618 mov r0, r3 10001232: 3710 adds r7, #16 10001234: 46bd mov sp, r7 10001236: bd80 pop {r7, pc} 10001238 : HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1) { 10001238: b580 push {r7, lr} 1000123a: b084 sub sp, #16 1000123c: af00 add r7, sp, #0 1000123e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the parameters */ assert_param(IS_RCC_PLL(pll1->PLLState)); if ((pll1->PLLState) != RCC_PLL_NONE) 10001240: 687b ldr r3, [r7, #4] 10001242: 681b ldr r3, [r3, #0] 10001244: 2b00 cmp r3, #0 10001246: f000 8174 beq.w 10001532 { /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/ if (!__IS_PLL1_IN_USE()) /* If not used then */ 1000124a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000124e: 6a1b ldr r3, [r3, #32] 10001250: f003 0303 and.w r3, r3, #3 10001254: 2b02 cmp r3, #2 10001256: d108 bne.n 1000126a 10001258: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000125c: 6a1b ldr r3, [r3, #32] 1000125e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001262: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001266: f000 8162 beq.w 1000152e 1000126a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000126e: 6a1b ldr r3, [r3, #32] 10001270: f003 0303 and.w r3, r3, #3 10001274: 2b03 cmp r3, #3 10001276: d108 bne.n 1000128a 10001278: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000127c: 6a1b ldr r3, [r3, #32] 1000127e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001282: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001286: f000 8152 beq.w 1000152e { if ((pll1->PLLState) == RCC_PLL_ON) 1000128a: 687b ldr r3, [r7, #4] 1000128c: 681b ldr r3, [r3, #0] 1000128e: 2b02 cmp r3, #2 10001290: f040 8123 bne.w 100014da assert_param(IS_RCC_PLLP1_VALUE(pll1->PLLP)); assert_param(IS_RCC_PLLQ1_VALUE(pll1->PLLQ)); assert_param(IS_RCC_PLLR1_VALUE(pll1->PLLR)); /*Disable the post-dividers*/ __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR); 10001294: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001298: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 1000129c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100012a0: f023 0370 bic.w r3, r3, #112 @ 0x70 100012a4: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Disable the main PLL. */ __HAL_RCC_PLL1_DISABLE(); 100012a8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100012ac: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100012b0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100012b4: f023 0301 bic.w r3, r3, #1 100012b8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Get Start Tick*/ tickstart = HAL_GetTick(); 100012bc: f7ff f89c bl 100003f8 100012c0: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET) 100012c2: e008 b.n 100012d6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 100012c4: f7ff f898 bl 100003f8 100012c8: 4602 mov r2, r0 100012ca: 68fb ldr r3, [r7, #12] 100012cc: 1ad3 subs r3, r2, r3 100012ce: 2b64 cmp r3, #100 @ 0x64 100012d0: d901 bls.n 100012d6 { return HAL_TIMEOUT; 100012d2: 2303 movs r3, #3 100012d4: e12e b.n 10001534 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET) 100012d6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100012da: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100012de: f003 0302 and.w r3, r3, #2 100012e2: 2b02 cmp r3, #2 100012e4: d0ee beq.n 100012c4 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN) -Fractional Division Enable (PLLxFRACNEN) -Fractional Division factor (FRACNx)*/ /* Do not change pll src if already in use */ if (__IS_PLL2_IN_USE()) 100012e6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100012ea: 6a5b ldr r3, [r3, #36] @ 0x24 100012ec: f003 0307 and.w r3, r3, #7 100012f0: 2b02 cmp r3, #2 100012f2: d112 bne.n 1000131a 100012f4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100012f8: 6a5b ldr r3, [r3, #36] @ 0x24 100012fa: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 100012fe: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001302: d10a bne.n 1000131a { if (pll1->PLLSource != __HAL_RCC_GET_PLL12_SOURCE()) 10001304: 687b ldr r3, [r7, #4] 10001306: 685a ldr r2, [r3, #4] 10001308: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000130c: 6a9b ldr r3, [r3, #40] @ 0x28 1000130e: f003 0303 and.w r3, r3, #3 10001312: 429a cmp r2, r3 10001314: d00c beq.n 10001330 { return HAL_ERROR; 10001316: 2301 movs r3, #1 10001318: e10c b.n 10001534 } } else { /* Configure PLL1 and PLL2 clock source */ __HAL_RCC_PLL12_SOURCE(pll1->PLLSource); 1000131a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000131e: 6a9b ldr r3, [r3, #40] @ 0x28 10001320: f023 0203 bic.w r2, r3, #3 10001324: 687b ldr r3, [r7, #4] 10001326: 685b ldr r3, [r3, #4] 10001328: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000132c: 4313 orrs r3, r2 1000132e: 628b str r3, [r1, #40] @ 0x28 } /* Wait till PLL SOURCE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL12SRCRDY) == RESET) 10001330: e008 b.n 10001344 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10001332: f7ff f861 bl 100003f8 10001336: 4602 mov r2, r0 10001338: 68fb ldr r3, [r7, #12] 1000133a: 1ad3 subs r3, r2, r3 1000133c: 2b64 cmp r3, #100 @ 0x64 1000133e: d901 bls.n 10001344 { return HAL_TIMEOUT; 10001340: 2303 movs r3, #3 10001342: e0f7 b.n 10001534 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL12SRCRDY) == RESET) 10001344: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001348: 6a9b ldr r3, [r3, #40] @ 0x28 1000134a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 1000134e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001352: d1ee bne.n 10001332 } } /* Configure the PLL1 multiplication and division factors. */ __HAL_RCC_PLL1_CONFIG( 10001354: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001358: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 1000135c: 4b77 ldr r3, [pc, #476] @ (1000153c ) 1000135e: 4013 ands r3, r2 10001360: 687a ldr r2, [r7, #4] 10001362: 68d2 ldr r2, [r2, #12] 10001364: 1e51 subs r1, r2, #1 10001366: 687a ldr r2, [r7, #4] 10001368: 6892 ldr r2, [r2, #8] 1000136a: 3a01 subs r2, #1 1000136c: 0412 lsls r2, r2, #16 1000136e: 430a orrs r2, r1 10001370: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001374: 4313 orrs r3, r2 10001376: f8c1 3084 str.w r3, [r1, #132] @ 0x84 1000137a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000137e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 10001382: f023 137f bic.w r3, r3, #8323199 @ 0x7f007f 10001386: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 1000138a: 687a ldr r2, [r7, #4] 1000138c: 6912 ldr r2, [r2, #16] 1000138e: 1e51 subs r1, r2, #1 10001390: 687a ldr r2, [r7, #4] 10001392: 6952 ldr r2, [r2, #20] 10001394: 3a01 subs r2, #1 10001396: 0212 lsls r2, r2, #8 10001398: 4311 orrs r1, r2 1000139a: 687a ldr r2, [r7, #4] 1000139c: 6992 ldr r2, [r2, #24] 1000139e: 3a01 subs r2, #1 100013a0: 0412 lsls r2, r2, #16 100013a2: 430a orrs r2, r1 100013a4: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100013a8: 4313 orrs r3, r2 100013aa: f8c1 3088 str.w r3, [r1, #136] @ 0x88 pll1->PLLQ, pll1->PLLR); /* Configure the Fractional Divider */ __HAL_RCC_PLL1FRACV_DISABLE(); /*Set FRACLE to '0' */ 100013ae: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100013b2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 100013b6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100013ba: f423 3380 bic.w r3, r3, #65536 @ 0x10000 100013be: f8c2 308c str.w r3, [r2, #140] @ 0x8c /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */ if ((pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll1->PLLMODE == RCC_PLL_INTEGER)) 100013c2: 687b ldr r3, [r7, #4] 100013c4: 6a5b ldr r3, [r3, #36] @ 0x24 100013c6: 2b02 cmp r3, #2 100013c8: d003 beq.n 100013d2 100013ca: 687b ldr r3, [r7, #4] 100013cc: 6a5b ldr r3, [r3, #36] @ 0x24 100013ce: 2b00 cmp r3, #0 100013d0: d10c bne.n 100013ec { /* Do not use the fractional divider */ __HAL_RCC_PLL1FRACV_CONFIG(0U); /* Set FRACV to '0' */ 100013d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100013d6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 100013da: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100013de: f423 437f bic.w r3, r3, #65280 @ 0xff00 100013e2: f023 03f8 bic.w r3, r3, #248 @ 0xf8 100013e6: f8c2 308c str.w r3, [r2, #140] @ 0x8c 100013ea: e00f b.n 1000140c } else { /* Configure PLL PLL1FRACV in fractional mode*/ __HAL_RCC_PLL1FRACV_CONFIG(pll1->PLLFRACV); 100013ec: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100013f0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 100013f4: f423 437f bic.w r3, r3, #65280 @ 0xff00 100013f8: f023 03f8 bic.w r3, r3, #248 @ 0xf8 100013fc: 687a ldr r2, [r7, #4] 100013fe: 6a12 ldr r2, [r2, #32] 10001400: 00d2 lsls r2, r2, #3 10001402: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001406: 4313 orrs r3, r2 10001408: f8c1 308c str.w r3, [r1, #140] @ 0x8c } __HAL_RCC_PLL1FRACV_ENABLE(); /* Set FRACLE to 1 */ 1000140c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001410: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 10001414: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001418: f443 3380 orr.w r3, r3, #65536 @ 0x10000 1000141c: f8c2 308c str.w r3, [r2, #140] @ 0x8c /* Configure the Spread Control */ if (pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) 10001420: 687b ldr r3, [r7, #4] 10001422: 6a5b ldr r3, [r3, #36] @ 0x24 10001424: 2b02 cmp r3, #2 10001426: d124 bne.n 10001472 assert_param(IS_RCC_SSCG_MODE(pll1->SSCG_MODE)); assert_param(IS_RCC_RPDFN_DIS(pll1->RPDFN_DIS)); assert_param(IS_RCC_TPDFN_DIS(pll1->TPDFN_DIS)); assert_param(IS_RCC_MOD_PER(pll1->MOD_PER)); __HAL_RCC_PLL1CSGCONFIG(pll1->MOD_PER, pll1->TPDFN_DIS, pll1->RPDFN_DIS, 10001428: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000142c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 10001430: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 10001434: 687b ldr r3, [r7, #4] 10001436: 6a99 ldr r1, [r3, #40] @ 0x28 10001438: 687b ldr r3, [r7, #4] 1000143a: 6b1b ldr r3, [r3, #48] @ 0x30 1000143c: 4319 orrs r1, r3 1000143e: 687b ldr r3, [r7, #4] 10001440: 6adb ldr r3, [r3, #44] @ 0x2c 10001442: 4319 orrs r1, r3 10001444: 687b ldr r3, [r7, #4] 10001446: 6b5b ldr r3, [r3, #52] @ 0x34 10001448: 4319 orrs r1, r3 1000144a: 687b ldr r3, [r7, #4] 1000144c: 6b9b ldr r3, [r3, #56] @ 0x38 1000144e: 041b lsls r3, r3, #16 10001450: 430b orrs r3, r1 10001452: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001456: 4313 orrs r3, r2 10001458: f8c1 3090 str.w r3, [r1, #144] @ 0x90 pll1->SSCG_MODE, pll1->INC_STEP); __HAL_RCC_PLL1_SSMODE_ENABLE(); 1000145c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001460: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 10001464: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001468: f043 0304 orr.w r3, r3, #4 1000146c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 10001470: e009 b.n 10001486 } else { __HAL_RCC_PLL1_SSMODE_DISABLE(); 10001472: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001476: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 1000147a: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 1000147e: f023 0304 bic.w r3, r3, #4 10001482: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Enable the PLL1. */ __HAL_RCC_PLL1_ENABLE(); 10001486: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000148a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 1000148e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001492: f043 0301 orr.w r3, r3, #1 10001496: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000149a: f7fe ffad bl 100003f8 1000149e: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET) 100014a0: e008 b.n 100014b4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 100014a2: f7fe ffa9 bl 100003f8 100014a6: 4602 mov r2, r0 100014a8: 68fb ldr r3, [r7, #12] 100014aa: 1ad3 subs r3, r2, r3 100014ac: 2b64 cmp r3, #100 @ 0x64 100014ae: d901 bls.n 100014b4 { return HAL_TIMEOUT; 100014b0: 2303 movs r3, #3 100014b2: e03f b.n 10001534 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET) 100014b4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100014b8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100014bc: f003 0302 and.w r3, r3, #2 100014c0: 2b02 cmp r3, #2 100014c2: d1ee bne.n 100014a2 } } /* Enable post-dividers */ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR); 100014c4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100014c8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100014cc: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100014d0: f043 0370 orr.w r3, r3, #112 @ 0x70 100014d4: f8c2 3080 str.w r3, [r2, #128] @ 0x80 if ((pll1->PLLState) == RCC_PLL_ON) 100014d8: e02b b.n 10001532 } else { /*Disable the post-dividers*/ __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR); 100014da: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100014de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100014e2: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100014e6: f023 0370 bic.w r3, r3, #112 @ 0x70 100014ea: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Disable the PLL1. */ __HAL_RCC_PLL1_DISABLE(); 100014ee: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100014f2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100014f6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100014fa: f023 0301 bic.w r3, r3, #1 100014fe: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001502: f7fe ff79 bl 100003f8 10001506: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET) 10001508: e008 b.n 1000151c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 1000150a: f7fe ff75 bl 100003f8 1000150e: 4602 mov r2, r0 10001510: 68fb ldr r3, [r7, #12] 10001512: 1ad3 subs r3, r2, r3 10001514: 2b64 cmp r3, #100 @ 0x64 10001516: d901 bls.n 1000151c { return HAL_TIMEOUT; 10001518: 2303 movs r3, #3 1000151a: e00b b.n 10001534 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET) 1000151c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001520: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 10001524: f003 0302 and.w r3, r3, #2 10001528: 2b02 cmp r3, #2 1000152a: d0ee beq.n 1000150a if ((pll1->PLLState) == RCC_PLL_ON) 1000152c: e001 b.n 10001532 } } } else { return HAL_ERROR; 1000152e: 2301 movs r3, #1 10001530: e000 b.n 10001534 } } return HAL_OK; 10001532: 2300 movs r3, #0 } 10001534: 4618 mov r0, r3 10001536: 3710 adds r7, #16 10001538: 46bd mov sp, r7 1000153a: bd80 pop {r7, pc} 1000153c: ffc0fe00 .word 0xffc0fe00 10001540 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct) { 10001540: b580 push {r7, lr} 10001542: b084 sub sp, #16 10001544: af00 add r7, sp, #0 10001546: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 10001548: 2300 movs r3, #0 1000154a: 73fb strb r3, [r7, #15] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 1000154c: 687b ldr r3, [r7, #4] 1000154e: 2b00 cmp r3, #0 10001550: d101 bne.n 10001556 { return HAL_ERROR; 10001552: 2301 movs r3, #1 10001554: e102 b.n 1000175c } assert_param(IS_RCC_CLOCKTYPETYPE(RCC_ClkInitStruct->ClockType)); /* Configure MPU block if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU) 10001556: 687b ldr r3, [r7, #4] 10001558: 681b ldr r3, [r3, #0] 1000155a: f003 0301 and.w r3, r3, #1 1000155e: 2b00 cmp r3, #0 10001560: d00b beq.n 1000157a { status = RCC_MPUConfig(&(RCC_ClkInitStruct->MPUInit)); 10001562: 687b ldr r3, [r7, #4] 10001564: 3304 adds r3, #4 10001566: 4618 mov r0, r3 10001568: f000 f8fc bl 10001764 1000156c: 4603 mov r3, r0 1000156e: 73fb strb r3, [r7, #15] if (status != HAL_OK) 10001570: 7bfb ldrb r3, [r7, #15] 10001572: 2b00 cmp r3, #0 10001574: d001 beq.n 1000157a { return status; 10001576: 7bfb ldrb r3, [r7, #15] 10001578: e0f0 b.n 1000175c } } /* Configure AXISS block if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_ACLK) == RCC_CLOCKTYPE_ACLK) 1000157a: 687b ldr r3, [r7, #4] 1000157c: 681b ldr r3, [r3, #0] 1000157e: f003 0302 and.w r3, r3, #2 10001582: 2b00 cmp r3, #0 10001584: d00b beq.n 1000159e { status = RCC_AXISSConfig(&(RCC_ClkInitStruct->AXISSInit)); 10001586: 687b ldr r3, [r7, #4] 10001588: 330c adds r3, #12 1000158a: 4618 mov r0, r3 1000158c: f000 f960 bl 10001850 10001590: 4603 mov r3, r0 10001592: 73fb strb r3, [r7, #15] if (status != HAL_OK) 10001594: 7bfb ldrb r3, [r7, #15] 10001596: 2b00 cmp r3, #0 10001598: d001 beq.n 1000159e { return status; 1000159a: 7bfb ldrb r3, [r7, #15] 1000159c: e0de b.n 1000175c } } /* Configure MCU block if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 1000159e: 687b ldr r3, [r7, #4] 100015a0: 681b ldr r3, [r3, #0] 100015a2: f003 0304 and.w r3, r3, #4 100015a6: 2b00 cmp r3, #0 100015a8: d00b beq.n 100015c2 { status = RCC_MCUConfig(&(RCC_ClkInitStruct->MCUInit)); 100015aa: 687b ldr r3, [r7, #4] 100015ac: 3314 adds r3, #20 100015ae: 4618 mov r0, r3 100015b0: f000 f9e6 bl 10001980 100015b4: 4603 mov r3, r0 100015b6: 73fb strb r3, [r7, #15] if (status != HAL_OK) 100015b8: 7bfb ldrb r3, [r7, #15] 100015ba: 2b00 cmp r3, #0 100015bc: d001 beq.n 100015c2 { return status; 100015be: 7bfb ldrb r3, [r7, #15] 100015c0: e0cc b.n 1000175c } } /* Configure APB4 divisor if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) 100015c2: 687b ldr r3, [r7, #4] 100015c4: 681b ldr r3, [r3, #0] 100015c6: f003 0308 and.w r3, r3, #8 100015ca: 2b00 cmp r3, #0 100015cc: d020 beq.n 10001610 { assert_param(IS_RCC_APB4DIV(RCC_ClkInitStruct->APB4_Div)); /* Set APB4 division factor */ __HAL_RCC_APB4_DIV(RCC_ClkInitStruct->APB4_Div); 100015ce: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100015d2: 6bdb ldr r3, [r3, #60] @ 0x3c 100015d4: f023 0207 bic.w r2, r3, #7 100015d8: 687b ldr r3, [r7, #4] 100015da: 69db ldr r3, [r3, #28] 100015dc: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100015e0: 4313 orrs r3, r2 100015e2: 63cb str r3, [r1, #60] @ 0x3c /* Get Start Tick*/ tickstart = HAL_GetTick(); 100015e4: f7fe ff08 bl 100003f8 100015e8: 60b8 str r0, [r7, #8] /* Wait till APB4 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB4DIVRDY) == RESET) 100015ea: e009 b.n 10001600 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 100015ec: f7fe ff04 bl 100003f8 100015f0: 4602 mov r2, r0 100015f2: 68bb ldr r3, [r7, #8] 100015f4: 1ad3 subs r3, r2, r3 100015f6: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 100015fa: d901 bls.n 10001600 { return HAL_TIMEOUT; 100015fc: 2303 movs r3, #3 100015fe: e0ad b.n 1000175c while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB4DIVRDY) == RESET) 10001600: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001604: 6bdb ldr r3, [r3, #60] @ 0x3c 10001606: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 1000160a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 1000160e: d1ed bne.n 100015ec } } } /* Configure APB5 divisor if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) 10001610: 687b ldr r3, [r7, #4] 10001612: 681b ldr r3, [r3, #0] 10001614: f003 0310 and.w r3, r3, #16 10001618: 2b00 cmp r3, #0 1000161a: d020 beq.n 1000165e { assert_param(IS_RCC_APB5DIV(RCC_ClkInitStruct->APB5_Div)); /* Set APB5 division factor */ __HAL_RCC_APB5_DIV(RCC_ClkInitStruct->APB5_Div); 1000161c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001620: 6c1b ldr r3, [r3, #64] @ 0x40 10001622: f023 0207 bic.w r2, r3, #7 10001626: 687b ldr r3, [r7, #4] 10001628: 6a1b ldr r3, [r3, #32] 1000162a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000162e: 4313 orrs r3, r2 10001630: 640b str r3, [r1, #64] @ 0x40 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001632: f7fe fee1 bl 100003f8 10001636: 60b8 str r0, [r7, #8] /* Wait till APB5 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB5DIVRDY) == RESET) 10001638: e009 b.n 1000164e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 1000163a: f7fe fedd bl 100003f8 1000163e: 4602 mov r2, r0 10001640: 68bb ldr r3, [r7, #8] 10001642: 1ad3 subs r3, r2, r3 10001644: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 10001648: d901 bls.n 1000164e { return HAL_TIMEOUT; 1000164a: 2303 movs r3, #3 1000164c: e086 b.n 1000175c while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB5DIVRDY) == RESET) 1000164e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001652: 6c1b ldr r3, [r3, #64] @ 0x40 10001654: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001658: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 1000165c: d1ed bne.n 1000163a } } } /* Configure APB1 divisor if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 1000165e: 687b ldr r3, [r7, #4] 10001660: 681b ldr r3, [r3, #0] 10001662: f003 0320 and.w r3, r3, #32 10001666: 2b00 cmp r3, #0 10001668: d023 beq.n 100016b2 { assert_param(IS_RCC_APB1DIV(RCC_ClkInitStruct->APB1_Div)); /* Set APB1 division factor */ __HAL_RCC_APB1_DIV(RCC_ClkInitStruct->APB1_Div); 1000166a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000166e: f8d3 3834 ldr.w r3, [r3, #2100] @ 0x834 10001672: f023 0207 bic.w r2, r3, #7 10001676: 687b ldr r3, [r7, #4] 10001678: 6a5b ldr r3, [r3, #36] @ 0x24 1000167a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000167e: 4313 orrs r3, r2 10001680: f8c1 3834 str.w r3, [r1, #2100] @ 0x834 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001684: f7fe feb8 bl 100003f8 10001688: 60b8 str r0, [r7, #8] /* Wait till APB1 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB1DIVRDY) == RESET) 1000168a: e009 b.n 100016a0 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 1000168c: f7fe feb4 bl 100003f8 10001690: 4602 mov r2, r0 10001692: 68bb ldr r3, [r7, #8] 10001694: 1ad3 subs r3, r2, r3 10001696: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 1000169a: d901 bls.n 100016a0 { return HAL_TIMEOUT; 1000169c: 2303 movs r3, #3 1000169e: e05d b.n 1000175c while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB1DIVRDY) == RESET) 100016a0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100016a4: f8d3 3834 ldr.w r3, [r3, #2100] @ 0x834 100016a8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 100016ac: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 100016b0: d1ec bne.n 1000168c } } } /* Configure APB2 divisor if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 100016b2: 687b ldr r3, [r7, #4] 100016b4: 681b ldr r3, [r3, #0] 100016b6: f003 0340 and.w r3, r3, #64 @ 0x40 100016ba: 2b00 cmp r3, #0 100016bc: d023 beq.n 10001706 { assert_param(IS_RCC_APB2DIV(RCC_ClkInitStruct->APB2_Div)); /* Set APB2 division factor */ __HAL_RCC_APB2_DIV(RCC_ClkInitStruct->APB2_Div); 100016be: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100016c2: f8d3 3838 ldr.w r3, [r3, #2104] @ 0x838 100016c6: f023 0207 bic.w r2, r3, #7 100016ca: 687b ldr r3, [r7, #4] 100016cc: 6a9b ldr r3, [r3, #40] @ 0x28 100016ce: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100016d2: 4313 orrs r3, r2 100016d4: f8c1 3838 str.w r3, [r1, #2104] @ 0x838 /* Get Start Tick*/ tickstart = HAL_GetTick(); 100016d8: f7fe fe8e bl 100003f8 100016dc: 60b8 str r0, [r7, #8] /* Wait till APB2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB2DIVRDY) == RESET) 100016de: e009 b.n 100016f4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 100016e0: f7fe fe8a bl 100003f8 100016e4: 4602 mov r2, r0 100016e6: 68bb ldr r3, [r7, #8] 100016e8: 1ad3 subs r3, r2, r3 100016ea: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 100016ee: d901 bls.n 100016f4 { return HAL_TIMEOUT; 100016f0: 2303 movs r3, #3 100016f2: e033 b.n 1000175c while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB2DIVRDY) == RESET) 100016f4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100016f8: f8d3 3838 ldr.w r3, [r3, #2104] @ 0x838 100016fc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001700: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001704: d1ec bne.n 100016e0 } } } /* Configure APB3 divisor if needed */ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) 10001706: 687b ldr r3, [r7, #4] 10001708: 681b ldr r3, [r3, #0] 1000170a: f003 0380 and.w r3, r3, #128 @ 0x80 1000170e: 2b00 cmp r3, #0 10001710: d023 beq.n 1000175a { assert_param(IS_RCC_APB3DIV(RCC_ClkInitStruct->APB3_Div)); /* Set APB3 division factor */ __HAL_RCC_APB3_DIV(RCC_ClkInitStruct->APB3_Div); 10001712: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001716: f8d3 383c ldr.w r3, [r3, #2108] @ 0x83c 1000171a: f023 0207 bic.w r2, r3, #7 1000171e: 687b ldr r3, [r7, #4] 10001720: 6adb ldr r3, [r3, #44] @ 0x2c 10001722: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001726: 4313 orrs r3, r2 10001728: f8c1 383c str.w r3, [r1, #2108] @ 0x83c /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000172c: f7fe fe64 bl 100003f8 10001730: 60b8 str r0, [r7, #8] /* Wait till APB3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB3DIVRDY) == RESET) 10001732: e009 b.n 10001748 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 10001734: f7fe fe60 bl 100003f8 10001738: 4602 mov r2, r0 1000173a: 68bb ldr r3, [r7, #8] 1000173c: 1ad3 subs r3, r2, r3 1000173e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 10001742: d901 bls.n 10001748 { return HAL_TIMEOUT; 10001744: 2303 movs r3, #3 10001746: e009 b.n 1000175c while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB3DIVRDY) == RESET) 10001748: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000174c: f8d3 383c ldr.w r3, [r3, #2108] @ 0x83c 10001750: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001754: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001758: d1ec bne.n 10001734 } } } return HAL_OK; 1000175a: 2300 movs r3, #0 } 1000175c: 4618 mov r0, r3 1000175e: 3710 adds r7, #16 10001760: 46bd mov sp, r7 10001762: bd80 pop {r7, pc} 10001764 : HAL_StatusTypeDef RCC_MPUConfig(RCC_MPUInitTypeDef *RCC_MPUInitStruct) { 10001764: b580 push {r7, lr} 10001766: b084 sub sp, #16 10001768: af00 add r7, sp, #0 1000176a: 6078 str r0, [r7, #4] uint32_t tickstart; assert_param(IS_RCC_MPUSOURCE(RCC_MPUInitStruct->MPU_Clock)); /* Ensure clock source is ready*/ switch (RCC_MPUInitStruct->MPU_Clock) 1000176c: 687b ldr r3, [r7, #4] 1000176e: 681b ldr r3, [r3, #0] 10001770: 2b03 cmp r3, #3 10001772: d840 bhi.n 100017f6 10001774: a201 add r2, pc, #4 @ (adr r2, 1000177c ) 10001776: f852 f023 ldr.w pc, [r2, r3, lsl #2] 1000177a: bf00 nop 1000177c: 1000178d .word 0x1000178d 10001780: 100017a1 .word 0x100017a1 10001784: 100017b7 .word 0x100017b7 10001788: 100017cb .word 0x100017cb { case (RCC_MPUSOURCE_HSI): { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 1000178c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001790: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10001794: f003 0301 and.w r3, r3, #1 10001798: 2b01 cmp r3, #1 1000179a: d02e beq.n 100017fa { return HAL_ERROR; 1000179c: 2301 movs r3, #1 1000179e: e053 b.n 10001848 } case (RCC_MPUSOURCE_HSE): { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 100017a0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100017a4: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 100017a8: f403 7380 and.w r3, r3, #256 @ 0x100 100017ac: f5b3 7f80 cmp.w r3, #256 @ 0x100 100017b0: d025 beq.n 100017fe { return HAL_ERROR; 100017b2: 2301 movs r3, #1 100017b4: e048 b.n 10001848 } case (RCC_MPUSOURCE_PLL1): { /* Check the PLL1 ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET) 100017b6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100017ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100017be: f003 0302 and.w r3, r3, #2 100017c2: 2b02 cmp r3, #2 100017c4: d01d beq.n 10001802 { return HAL_ERROR; 100017c6: 2301 movs r3, #1 100017c8: e03e b.n 10001848 case (RCC_MPUSOURCE_MPUDIV): { assert_param(IS_RCC_MPUDIV(RCC_MPUInitStruct->MPU_Div)); /* Check the PLL1 ready flag (as PLL1_P is the MPUDIV source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET) 100017ca: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100017ce: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 100017d2: f003 0302 and.w r3, r3, #2 100017d6: 2b02 cmp r3, #2 100017d8: d001 beq.n 100017de { return HAL_ERROR; 100017da: 2301 movs r3, #1 100017dc: e034 b.n 10001848 } /* Set MPU division factor */ __HAL_RCC_MPU_DIV(RCC_MPUInitStruct->MPU_Div); 100017de: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100017e2: 6adb ldr r3, [r3, #44] @ 0x2c 100017e4: f023 0207 bic.w r2, r3, #7 100017e8: 687b ldr r3, [r7, #4] 100017ea: 685b ldr r3, [r3, #4] 100017ec: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100017f0: 4313 orrs r3, r2 100017f2: 62cb str r3, [r1, #44] @ 0x2c break; 100017f4: e006 b.n 10001804 } default: /* This case is impossible */ return HAL_ERROR; 100017f6: 2301 movs r3, #1 100017f8: e026 b.n 10001848 break; 100017fa: bf00 nop 100017fc: e002 b.n 10001804 break; 100017fe: bf00 nop 10001800: e000 b.n 10001804 break; 10001802: bf00 nop break; } /* Set MPU clock source */ __HAL_RCC_MPU_SOURCE(RCC_MPUInitStruct->MPU_Clock); 10001804: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001808: 6a1b ldr r3, [r3, #32] 1000180a: f023 0203 bic.w r2, r3, #3 1000180e: 687b ldr r3, [r7, #4] 10001810: 681b ldr r3, [r3, #0] 10001812: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001816: 4313 orrs r3, r2 10001818: 620b str r3, [r1, #32] /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000181a: f7fe fded bl 100003f8 1000181e: 60f8 str r0, [r7, #12] /* Wait till MPU is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) == RESET) 10001820: e009 b.n 10001836 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 10001822: f7fe fde9 bl 100003f8 10001826: 4602 mov r2, r0 10001828: 68fb ldr r3, [r7, #12] 1000182a: 1ad3 subs r3, r2, r3 1000182c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 10001830: d901 bls.n 10001836 { return HAL_TIMEOUT; 10001832: 2303 movs r3, #3 10001834: e008 b.n 10001848 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) == RESET) 10001836: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000183a: 6a1b ldr r3, [r3, #32] 1000183c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001840: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001844: d1ed bne.n 10001822 /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); #endif return HAL_OK; 10001846: 2300 movs r3, #0 } 10001848: 4618 mov r0, r3 1000184a: 3710 adds r7, #16 1000184c: 46bd mov sp, r7 1000184e: bd80 pop {r7, pc} 10001850 : HAL_StatusTypeDef RCC_AXISSConfig(RCC_AXISSInitTypeDef *RCC_AXISSInitStruct) { 10001850: b580 push {r7, lr} 10001852: b084 sub sp, #16 10001854: af00 add r7, sp, #0 10001856: 6078 str r0, [r7, #4] assert_param(IS_RCC_AXISSOURCE(RCC_AXISSInitStruct->AXI_Clock)); assert_param(IS_RCC_AXIDIV(RCC_AXISSInitStruct->AXI_Div)); /* Ensure clock source is ready*/ switch (RCC_AXISSInitStruct->AXI_Clock) 10001858: 687b ldr r3, [r7, #4] 1000185a: 681b ldr r3, [r3, #0] 1000185c: 2b02 cmp r3, #2 1000185e: d01b beq.n 10001898 10001860: 2b02 cmp r3, #2 10001862: d823 bhi.n 100018ac 10001864: 2b00 cmp r3, #0 10001866: d002 beq.n 1000186e 10001868: 2b01 cmp r3, #1 1000186a: d00a beq.n 10001882 } break; } default: break; 1000186c: e01e b.n 100018ac if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 1000186e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001872: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10001876: f003 0301 and.w r3, r3, #1 1000187a: 2b01 cmp r3, #1 1000187c: d018 beq.n 100018b0 return HAL_ERROR; 1000187e: 2301 movs r3, #1 10001880: e079 b.n 10001976 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 10001882: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001886: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 1000188a: f403 7380 and.w r3, r3, #256 @ 0x100 1000188e: f5b3 7f80 cmp.w r3, #256 @ 0x100 10001892: d00f beq.n 100018b4 return HAL_ERROR; 10001894: 2301 movs r3, #1 10001896: e06e b.n 10001976 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 10001898: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000189c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 100018a0: f003 0302 and.w r3, r3, #2 100018a4: 2b02 cmp r3, #2 100018a6: d007 beq.n 100018b8 return HAL_ERROR; 100018a8: 2301 movs r3, #1 100018aa: e064 b.n 10001976 break; 100018ac: bf00 nop 100018ae: e004 b.n 100018ba break; 100018b0: bf00 nop 100018b2: e002 b.n 100018ba break; 100018b4: bf00 nop 100018b6: e000 b.n 100018ba break; 100018b8: bf00 nop } /* Set AXISS clock source */ __HAL_RCC_AXISS_SOURCE(RCC_AXISSInitStruct->AXI_Clock); 100018ba: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100018be: 6a5b ldr r3, [r3, #36] @ 0x24 100018c0: f023 0207 bic.w r2, r3, #7 100018c4: 687b ldr r3, [r7, #4] 100018c6: 681b ldr r3, [r3, #0] 100018c8: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100018cc: 4313 orrs r3, r2 100018ce: 624b str r3, [r1, #36] @ 0x24 if (RCC_AXISSInitStruct->AXI_Clock != RCC_AXISSOURCE_OFF) 100018d0: 687b ldr r3, [r7, #4] 100018d2: 681b ldr r3, [r3, #0] 100018d4: 2b03 cmp r3, #3 100018d6: d016 beq.n 10001906 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 100018d8: f7fe fd8e bl 100003f8 100018dc: 60f8 str r0, [r7, #12] /* Wait till AXISS is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) == RESET) 100018de: e009 b.n 100018f4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 100018e0: f7fe fd8a bl 100003f8 100018e4: 4602 mov r2, r0 100018e6: 68fb ldr r3, [r7, #12] 100018e8: 1ad3 subs r3, r2, r3 100018ea: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 100018ee: d901 bls.n 100018f4 { return HAL_TIMEOUT; 100018f0: 2303 movs r3, #3 100018f2: e040 b.n 10001976 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) == RESET) 100018f4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100018f8: 6a5b ldr r3, [r3, #36] @ 0x24 100018fa: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 100018fe: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001902: d1ed bne.n 100018e0 10001904: e015 b.n 10001932 } else { // RCC_AXISSOURCE_OFF case /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001906: f7fe fd77 bl 100003f8 1000190a: 60f8 str r0, [r7, #12] /* Wait till AXISS is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) != RESET) 1000190c: e009 b.n 10001922 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 1000190e: f7fe fd73 bl 100003f8 10001912: 4602 mov r2, r0 10001914: 68fb ldr r3, [r7, #12] 10001916: 1ad3 subs r3, r2, r3 10001918: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 1000191c: d901 bls.n 10001922 { return HAL_TIMEOUT; 1000191e: 2303 movs r3, #3 10001920: e029 b.n 10001976 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) != RESET) 10001922: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001926: 6a5b ldr r3, [r3, #36] @ 0x24 10001928: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 1000192c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001930: d0ed beq.n 1000190e } } } /* Set AXISS division factor */ __HAL_RCC_AXI_DIV(RCC_AXISSInitStruct->AXI_Div); 10001932: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001936: 6b1b ldr r3, [r3, #48] @ 0x30 10001938: f023 0207 bic.w r2, r3, #7 1000193c: 687b ldr r3, [r7, #4] 1000193e: 685b ldr r3, [r3, #4] 10001940: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001944: 4313 orrs r3, r2 10001946: 630b str r3, [r1, #48] @ 0x30 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001948: f7fe fd56 bl 100003f8 1000194c: 60f8 str r0, [r7, #12] /* Wait till AXISS is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXIDIVRDY) == RESET) 1000194e: e009 b.n 10001964 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 10001950: f7fe fd52 bl 100003f8 10001954: 4602 mov r2, r0 10001956: 68fb ldr r3, [r7, #12] 10001958: 1ad3 subs r3, r2, r3 1000195a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 1000195e: d901 bls.n 10001964 { return HAL_TIMEOUT; 10001960: 2303 movs r3, #3 10001962: e008 b.n 10001976 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXIDIVRDY) == RESET) 10001964: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001968: 6b1b ldr r3, [r3, #48] @ 0x30 1000196a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 1000196e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001972: d1ed bne.n 10001950 } } return HAL_OK; 10001974: 2300 movs r3, #0 } 10001976: 4618 mov r0, r3 10001978: 3710 adds r7, #16 1000197a: 46bd mov sp, r7 1000197c: bd80 pop {r7, pc} ... 10001980 : HAL_StatusTypeDef RCC_MCUConfig(RCC_MCUInitTypeDef *MCUInitStruct) { 10001980: b580 push {r7, lr} 10001982: b084 sub sp, #16 10001984: af00 add r7, sp, #0 10001986: 6078 str r0, [r7, #4] assert_param(IS_RCC_MCUSSOURCE(MCUInitStruct->MCU_Clock)); assert_param(IS_RCC_MCUDIV(MCUInitStruct->MCU_Div)); /* Ensure clock source is ready*/ switch (MCUInitStruct->MCU_Clock) 10001988: 687b ldr r3, [r7, #4] 1000198a: 681b ldr r3, [r3, #0] 1000198c: 2b03 cmp r3, #3 1000198e: d834 bhi.n 100019fa 10001990: a201 add r2, pc, #4 @ (adr r2, 10001998 ) 10001992: f852 f023 ldr.w pc, [r2, r3, lsl #2] 10001996: bf00 nop 10001998: 100019a9 .word 0x100019a9 1000199c: 100019bd .word 0x100019bd 100019a0: 100019d3 .word 0x100019d3 100019a4: 100019e7 .word 0x100019e7 { case (RCC_MCUSSOURCE_HSI): { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 100019a8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100019ac: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 100019b0: f003 0301 and.w r3, r3, #1 100019b4: 2b01 cmp r3, #1 100019b6: d022 beq.n 100019fe { return HAL_ERROR; 100019b8: 2301 movs r3, #1 100019ba: e081 b.n 10001ac0 } case (RCC_MCUSSOURCE_HSE): { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 100019bc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100019c0: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 100019c4: f403 7380 and.w r3, r3, #256 @ 0x100 100019c8: f5b3 7f80 cmp.w r3, #256 @ 0x100 100019cc: d019 beq.n 10001a02 { return HAL_ERROR; 100019ce: 2301 movs r3, #1 100019d0: e076 b.n 10001ac0 } case (RCC_MCUSSOURCE_CSI): { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET) 100019d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100019d6: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 100019da: f003 0310 and.w r3, r3, #16 100019de: 2b10 cmp r3, #16 100019e0: d011 beq.n 10001a06 { return HAL_ERROR; 100019e2: 2301 movs r3, #1 100019e4: e06c b.n 10001ac0 } case (RCC_MCUSSOURCE_PLL3): { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET) 100019e6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100019ea: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 100019ee: f003 0302 and.w r3, r3, #2 100019f2: 2b02 cmp r3, #2 100019f4: d009 beq.n 10001a0a { return HAL_ERROR; 100019f6: 2301 movs r3, #1 100019f8: e062 b.n 10001ac0 } break; } default: break; 100019fa: bf00 nop 100019fc: e006 b.n 10001a0c break; 100019fe: bf00 nop 10001a00: e004 b.n 10001a0c break; 10001a02: bf00 nop 10001a04: e002 b.n 10001a0c break; 10001a06: bf00 nop 10001a08: e000 b.n 10001a0c break; 10001a0a: bf00 nop } /* Set MCU clock source */ __HAL_RCC_MCU_SOURCE(MCUInitStruct->MCU_Clock); 10001a0c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001a10: 6c9b ldr r3, [r3, #72] @ 0x48 10001a12: f023 0203 bic.w r2, r3, #3 10001a16: 687b ldr r3, [r7, #4] 10001a18: 681b ldr r3, [r3, #0] 10001a1a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001a1e: 4313 orrs r3, r2 10001a20: 648b str r3, [r1, #72] @ 0x48 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001a22: f7fe fce9 bl 100003f8 10001a26: 60f8 str r0, [r7, #12] /* Wait till MCU is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) == RESET) 10001a28: e009 b.n 10001a3e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 10001a2a: f7fe fce5 bl 100003f8 10001a2e: 4602 mov r2, r0 10001a30: 68fb ldr r3, [r7, #12] 10001a32: 1ad3 subs r3, r2, r3 10001a34: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 10001a38: d901 bls.n 10001a3e { return HAL_TIMEOUT; 10001a3a: 2303 movs r3, #3 10001a3c: e040 b.n 10001ac0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) == RESET) 10001a3e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001a42: 6c9b ldr r3, [r3, #72] @ 0x48 10001a44: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001a48: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001a4c: d1ed bne.n 10001a2a } } #ifdef CORE_CM4 /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); 10001a4e: f000 f954 bl 10001cfa 10001a52: 4603 mov r3, r0 10001a54: 4a1c ldr r2, [pc, #112] @ (10001ac8 ) 10001a56: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 10001a58: 4b1c ldr r3, [pc, #112] @ (10001acc ) 10001a5a: 681b ldr r3, [r3, #0] 10001a5c: 4618 mov r0, r3 10001a5e: f7fe fc81 bl 10000364 #endif /* Set MCU division factor */ __HAL_RCC_MCU_DIV(MCUInitStruct->MCU_Div); 10001a62: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001a66: f8d3 3830 ldr.w r3, [r3, #2096] @ 0x830 10001a6a: f023 020f bic.w r2, r3, #15 10001a6e: 687b ldr r3, [r7, #4] 10001a70: 685b ldr r3, [r3, #4] 10001a72: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001a76: 4313 orrs r3, r2 10001a78: f8c1 3830 str.w r3, [r1, #2096] @ 0x830 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001a7c: f7fe fcbc bl 100003f8 10001a80: 60f8 str r0, [r7, #12] /* Wait till MCU is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUDIVRDY) == RESET) 10001a82: e009 b.n 10001a98 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 10001a84: f7fe fcb8 bl 100003f8 10001a88: 4602 mov r2, r0 10001a8a: 68fb ldr r3, [r7, #12] 10001a8c: 1ad3 subs r3, r2, r3 10001a8e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 10001a92: d901 bls.n 10001a98 { return HAL_TIMEOUT; 10001a94: 2303 movs r3, #3 10001a96: e013 b.n 10001ac0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUDIVRDY) == RESET) 10001a98: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001a9c: f8d3 3830 ldr.w r3, [r3, #2096] @ 0x830 10001aa0: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001aa4: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001aa8: d1ec bne.n 10001a84 } } #ifdef CORE_CM4 /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq(); 10001aaa: f000 f926 bl 10001cfa 10001aae: 4603 mov r3, r0 10001ab0: 4a05 ldr r2, [pc, #20] @ (10001ac8 ) 10001ab2: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 10001ab4: 4b05 ldr r3, [pc, #20] @ (10001acc ) 10001ab6: 681b ldr r3, [r3, #0] 10001ab8: 4618 mov r0, r3 10001aba: f7fe fc53 bl 10000364 #endif return HAL_OK; 10001abe: 2300 movs r3, #0 } 10001ac0: 4618 mov r0, r3 10001ac2: 3710 adds r7, #16 10001ac4: 46bd mov sp, r7 10001ac6: bd80 pop {r7, pc} 10001ac8: 10020000 .word 0x10020000 10001acc: 10020004 .word 0x10020004 10001ad0 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ __weak void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 10001ad0: b480 push {r7} 10001ad2: b089 sub sp, #36 @ 0x24 10001ad4: af00 add r7, sp, #0 10001ad6: 6078 str r0, [r7, #4] uint32_t pllsource = 0, pll3m = 1, pll3fracen = 0, hsivalue = 0; 10001ad8: 2300 movs r3, #0 10001ada: 61bb str r3, [r7, #24] 10001adc: 2301 movs r3, #1 10001ade: 617b str r3, [r7, #20] 10001ae0: 2300 movs r3, #0 10001ae2: 613b str r3, [r7, #16] 10001ae4: 2300 movs r3, #0 10001ae6: 60fb str r3, [r7, #12] float fracn1, pll3vco = 0; 10001ae8: f04f 0300 mov.w r3, #0 10001aec: 61fb str r3, [r7, #28] pllsource = __HAL_RCC_GET_PLL3_SOURCE(); 10001aee: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001af2: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 10001af6: f003 0303 and.w r3, r3, #3 10001afa: 61bb str r3, [r7, #24] pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U; 10001afc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b00: f8d3 3884 ldr.w r3, [r3, #2180] @ 0x884 10001b04: 0c1b lsrs r3, r3, #16 10001b06: f003 033f and.w r3, r3, #63 @ 0x3f 10001b0a: 3301 adds r3, #1 10001b0c: 617b str r3, [r7, #20] pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> RCC_PLL3FRACR_FRACLE_Pos; 10001b0e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b12: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10001b16: 0c1b lsrs r3, r3, #16 10001b18: f003 0301 and.w r3, r3, #1 10001b1c: 613b str r3, [r7, #16] fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos)); 10001b1e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b22: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10001b26: 08db lsrs r3, r3, #3 10001b28: f3c3 030c ubfx r3, r3, #0, #13 10001b2c: 693a ldr r2, [r7, #16] 10001b2e: fb02 f303 mul.w r3, r2, r3 10001b32: ee07 3a90 vmov s15, r3 10001b36: eef8 7a67 vcvt.f32.u32 s15, s15 10001b3a: edc7 7a02 vstr s15, [r7, #8] pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000)); //Intermediary value 10001b3e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b42: f8d3 3884 ldr.w r3, [r3, #2180] @ 0x884 10001b46: f3c3 0308 ubfx r3, r3, #0, #9 10001b4a: 3301 adds r3, #1 10001b4c: ee07 3a90 vmov s15, r3 10001b50: eeb8 7a67 vcvt.f32.u32 s14, s15 10001b54: edd7 6a02 vldr s13, [r7, #8] 10001b58: ed9f 6a56 vldr s12, [pc, #344] @ 10001cb4 10001b5c: eec6 7a86 vdiv.f32 s15, s13, s12 10001b60: ee77 7a27 vadd.f32 s15, s14, s15 10001b64: edc7 7a07 vstr s15, [r7, #28] switch (pllsource) 10001b68: 69bb ldr r3, [r7, #24] 10001b6a: 2b03 cmp r3, #3 10001b6c: d85b bhi.n 10001c26 10001b6e: a201 add r2, pc, #4 @ (adr r2, 10001b74 ) 10001b70: f852 f023 ldr.w pc, [r2, r3, lsl #2] 10001b74: 10001b85 .word 0x10001b85 10001b78: 10001be3 .word 0x10001be3 10001b7c: 10001c01 .word 0x10001c01 10001b80: 10001c1f .word 0x10001c1f { case RCC_PLL3SOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U) 10001b84: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b88: f8d3 3808 ldr.w r3, [r3, #2056] @ 0x808 10001b8c: f003 0304 and.w r3, r3, #4 10001b90: 2b04 cmp r3, #4 10001b92: d117 bne.n 10001bc4 { hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV()); 10001b94: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001b98: 699b ldr r3, [r3, #24] 10001b9a: f003 0303 and.w r3, r3, #3 10001b9e: 4a46 ldr r2, [pc, #280] @ (10001cb8 ) 10001ba0: fa22 f303 lsr.w r3, r2, r3 10001ba4: 60fb str r3, [r7, #12] pll3vco *= (float)(hsivalue / pll3m); 10001ba6: 68fa ldr r2, [r7, #12] 10001ba8: 697b ldr r3, [r7, #20] 10001baa: fbb2 f3f3 udiv r3, r2, r3 10001bae: ee07 3a90 vmov s15, r3 10001bb2: eef8 7a67 vcvt.f32.u32 s15, s15 10001bb6: ed97 7a07 vldr s14, [r7, #28] 10001bba: ee67 7a27 vmul.f32 s15, s14, s15 10001bbe: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco *= (float)(HSI_VALUE / pll3m); } break; 10001bc2: e030 b.n 10001c26 pll3vco *= (float)(HSI_VALUE / pll3m); 10001bc4: 4a3c ldr r2, [pc, #240] @ (10001cb8 ) 10001bc6: 697b ldr r3, [r7, #20] 10001bc8: fbb2 f3f3 udiv r3, r2, r3 10001bcc: ee07 3a90 vmov s15, r3 10001bd0: eef8 7a67 vcvt.f32.u32 s15, s15 10001bd4: ed97 7a07 vldr s14, [r7, #28] 10001bd8: ee67 7a27 vmul.f32 s15, s14, s15 10001bdc: edc7 7a07 vstr s15, [r7, #28] break; 10001be0: e021 b.n 10001c26 case RCC_PLL3SOURCE_HSE: /* HSE used as PLL clock source */ pll3vco *= (float)(HSE_VALUE / pll3m); 10001be2: 4a36 ldr r2, [pc, #216] @ (10001cbc ) 10001be4: 697b ldr r3, [r7, #20] 10001be6: fbb2 f3f3 udiv r3, r2, r3 10001bea: ee07 3a90 vmov s15, r3 10001bee: eef8 7a67 vcvt.f32.u32 s15, s15 10001bf2: ed97 7a07 vldr s14, [r7, #28] 10001bf6: ee67 7a27 vmul.f32 s15, s14, s15 10001bfa: edc7 7a07 vstr s15, [r7, #28] break; 10001bfe: e012 b.n 10001c26 case RCC_PLL3SOURCE_CSI: /* CSI used as PLL clock source */ pll3vco *= (float)(CSI_VALUE / pll3m); 10001c00: 4a2f ldr r2, [pc, #188] @ (10001cc0 ) 10001c02: 697b ldr r3, [r7, #20] 10001c04: fbb2 f3f3 udiv r3, r2, r3 10001c08: ee07 3a90 vmov s15, r3 10001c0c: eef8 7a67 vcvt.f32.u32 s15, s15 10001c10: ed97 7a07 vldr s14, [r7, #28] 10001c14: ee67 7a27 vmul.f32 s15, s14, s15 10001c18: edc7 7a07 vstr s15, [r7, #28] break; 10001c1c: e003 b.n 10001c26 case RCC_PLL3SOURCE_OFF: /* No clock source for PLL */ pll3vco = 0; 10001c1e: f04f 0300 mov.w r3, #0 10001c22: 61fb str r3, [r7, #28] break; 10001c24: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) >> RCC_PLL3CFGR2_DIVP_Pos) + 1U))); 10001c26: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001c2a: f8d3 3888 ldr.w r3, [r3, #2184] @ 0x888 10001c2e: f003 037f and.w r3, r3, #127 @ 0x7f 10001c32: 3301 adds r3, #1 10001c34: ee07 3a90 vmov s15, r3 10001c38: eeb8 7a67 vcvt.f32.u32 s14, s15 10001c3c: edd7 6a07 vldr s13, [r7, #28] 10001c40: eec6 7a87 vdiv.f32 s15, s13, s14 10001c44: eefc 7ae7 vcvt.u32.f32 s15, s15 10001c48: ee17 2a90 vmov r2, s15 10001c4c: 687b ldr r3, [r7, #4] 10001c4e: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVQ) >> RCC_PLL3CFGR2_DIVQ_Pos) + 1U))); 10001c50: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001c54: f8d3 3888 ldr.w r3, [r3, #2184] @ 0x888 10001c58: 0a1b lsrs r3, r3, #8 10001c5a: f003 037f and.w r3, r3, #127 @ 0x7f 10001c5e: 3301 adds r3, #1 10001c60: ee07 3a90 vmov s15, r3 10001c64: eeb8 7a67 vcvt.f32.u32 s14, s15 10001c68: edd7 6a07 vldr s13, [r7, #28] 10001c6c: eec6 7a87 vdiv.f32 s15, s13, s14 10001c70: eefc 7ae7 vcvt.u32.f32 s15, s15 10001c74: ee17 2a90 vmov r2, s15 10001c78: 687b ldr r3, [r7, #4] 10001c7a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1U))); 10001c7c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001c80: f8d3 3888 ldr.w r3, [r3, #2184] @ 0x888 10001c84: 0c1b lsrs r3, r3, #16 10001c86: f003 037f and.w r3, r3, #127 @ 0x7f 10001c8a: 3301 adds r3, #1 10001c8c: ee07 3a90 vmov s15, r3 10001c90: eeb8 7a67 vcvt.f32.u32 s14, s15 10001c94: edd7 6a07 vldr s13, [r7, #28] 10001c98: eec6 7a87 vdiv.f32 s15, s13, s14 10001c9c: eefc 7ae7 vcvt.u32.f32 s15, s15 10001ca0: ee17 2a90 vmov r2, s15 10001ca4: 687b ldr r3, [r7, #4] 10001ca6: 609a str r2, [r3, #8] } 10001ca8: bf00 nop 10001caa: 3724 adds r7, #36 @ 0x24 10001cac: 46bd mov sp, r7 10001cae: f85d 7b04 ldr.w r7, [sp], #4 10001cb2: 4770 bx lr 10001cb4: 46000000 .word 0x46000000 10001cb8: 03d09000 .word 0x03d09000 10001cbc: 016e3600 .word 0x016e3600 10001cc0: 003d0900 .word 0x003d0900 10001cc4 : * @note Each time MCU changes, this function must be called to update the * right MCU value. Otherwise, any configuration based on this function will be incorrect. * @retval MCU frequency */ uint32_t HAL_RCC_GetMCUFreq(void) { 10001cc4: b580 push {r7, lr} 10001cc6: b082 sub sp, #8 10001cc8: af00 add r7, sp, #0 uint32_t mcudiv = 0; 10001cca: 2300 movs r3, #0 10001ccc: 607b str r3, [r7, #4] /* Compute MCU frequency ---------------------------*/ mcudiv = __HAL_RCC_GET_MCU_DIV(); 10001cce: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001cd2: f8d3 3830 ldr.w r3, [r3, #2096] @ 0x830 10001cd6: f003 030f and.w r3, r3, #15 10001cda: 607b str r3, [r7, #4] if (mcudiv > RCC_MCU_DIV512) 10001cdc: 687b ldr r3, [r7, #4] 10001cde: 2b09 cmp r3, #9 10001ce0: d901 bls.n 10001ce6 { mcudiv = RCC_MCU_DIV512; 10001ce2: 2309 movs r3, #9 10001ce4: 607b str r3, [r7, #4] } return HAL_RCC_GetMCUSSFreq() >> mcudiv; 10001ce6: f000 f80f bl 10001d08 10001cea: 4602 mov r2, r0 10001cec: 687b ldr r3, [r7, #4] 10001cee: fa22 f303 lsr.w r3, r2, r3 } 10001cf2: 4618 mov r0, r3 10001cf4: 3708 adds r7, #8 10001cf6: 46bd mov sp, r7 10001cf8: bd80 pop {r7, pc} 10001cfa : * frequency in the chip. It is calculated based on the predefined * constants and the selected clock source * @retval System Core frequency */ uint32_t HAL_RCC_GetSystemCoreClockFreq(void) { 10001cfa: b580 push {r7, lr} 10001cfc: af00 add r7, sp, #0 #ifdef CORE_CA7 return HAL_RCC_GetMPUSSFreq(); #else /* CORE_CM4 */ return HAL_RCC_GetMCUFreq(); 10001cfe: f7ff ffe1 bl 10001cc4 10001d02: 4603 mov r3, r0 #endif } 10001d04: 4618 mov r0, r3 10001d06: bd80 pop {r7, pc} 10001d08 : return axissfreq; } uint32_t HAL_RCC_GetMCUSSFreq() { 10001d08: b580 push {r7, lr} 10001d0a: b084 sub sp, #16 10001d0c: af00 add r7, sp, #0 uint32_t mcussfreq = 0; 10001d0e: 2300 movs r3, #0 10001d10: 60fb str r3, [r7, #12] PLL3_ClocksTypeDef pll3_clocks; switch (__HAL_RCC_GET_MCU_SOURCE()) 10001d12: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001d16: 6c9b ldr r3, [r3, #72] @ 0x48 10001d18: f003 0303 and.w r3, r3, #3 10001d1c: 2b03 cmp r3, #3 10001d1e: d822 bhi.n 10001d66 10001d20: a201 add r2, pc, #4 @ (adr r2, 10001d28 ) 10001d22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 10001d26: bf00 nop 10001d28: 10001d47 .word 0x10001d47 10001d2c: 10001d5b .word 0x10001d5b 10001d30: 10001d61 .word 0x10001d61 10001d34: 10001d39 .word 0x10001d39 { case RCC_MCUSSOURCE_PLL3: HAL_RCC_GetPLL3ClockFreq(&pll3_clocks); 10001d38: 463b mov r3, r7 10001d3a: 4618 mov r0, r3 10001d3c: f7ff fec8 bl 10001ad0 mcussfreq = pll3_clocks.PLL3_P_Frequency; 10001d40: 683b ldr r3, [r7, #0] 10001d42: 60fb str r3, [r7, #12] break; 10001d44: e00f b.n 10001d66 case RCC_MCUSSOURCE_HSI: mcussfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV()); 10001d46: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001d4a: 699b ldr r3, [r3, #24] 10001d4c: f003 0303 and.w r3, r3, #3 10001d50: 4a07 ldr r2, [pc, #28] @ (10001d70 ) 10001d52: fa22 f303 lsr.w r3, r2, r3 10001d56: 60fb str r3, [r7, #12] break; 10001d58: e005 b.n 10001d66 case RCC_MCUSSOURCE_HSE: mcussfreq = HSE_VALUE; 10001d5a: 4b06 ldr r3, [pc, #24] @ (10001d74 ) 10001d5c: 60fb str r3, [r7, #12] break; 10001d5e: e002 b.n 10001d66 case RCC_MCUSSOURCE_CSI: mcussfreq = CSI_VALUE; 10001d60: 4b05 ldr r3, [pc, #20] @ (10001d78 ) 10001d62: 60fb str r3, [r7, #12] break; 10001d64: bf00 nop } return mcussfreq; 10001d66: 68fb ldr r3, [r7, #12] } 10001d68: 4618 mov r0, r3 10001d6a: 3710 adds r7, #16 10001d6c: 46bd mov sp, r7 10001d6e: bd80 pop {r7, pc} 10001d70: 03d09000 .word 0x03d09000 10001d74: 016e3600 .word 0x016e3600 10001d78: 003d0900 .word 0x003d0900 10001d7c : * @brief This function handles the RCC Wake up interrupt (rcc_mcu_wkup_irq/rcc_mpu_wkup_irq) * @note This API should be called under the RCC_WAKEUP_Handler(). * @retval None */ void HAL_RCC_WAKEUP_IRQHandler(void) { 10001d7c: b580 push {r7, lr} 10001d7e: af00 add r7, sp, #0 /* Check RCC WKUP flag is set */ if (__HAL_RCC_GET_IT(RCC_IT_WKUP) != RESET) 10001d80: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001d84: f8d3 3c18 ldr.w r3, [r3, #3096] @ 0xc18 10001d88: f403 1380 and.w r3, r3, #1048576 @ 0x100000 10001d8c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 10001d90: d107 bne.n 10001da2 { /* Clear the RCC WKUP flag bit */ __HAL_RCC_CLEAR_IT(RCC_IT_WKUP); 10001d92: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001d96: f44f 1280 mov.w r2, #1048576 @ 0x100000 10001d9a: f8c3 2c18 str.w r2, [r3, #3096] @ 0xc18 /* RCC WKUP interrupt user callback */ HAL_RCC_WAKEUP_Callback(); 10001d9e: f000 f802 bl 10001da6 } } 10001da2: bf00 nop 10001da4: bd80 pop {r7, pc} 10001da6 : /** * @brief RCC WAKEUP interrupt callback * @retval None */ __weak void HAL_RCC_WAKEUP_Callback(void) { 10001da6: b480 push {r7} 10001da8: af00 add r7, sp, #0 /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_WAKEUP_Callback could be implemented in the user file */ } 10001daa: bf00 nop 10001dac: 46bd mov sp, r7 10001dae: f85d 7b04 ldr.w r7, [sp], #4 10001db2: 4770 bx lr 10001db4 : * * @retval HAL status */ HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2) { 10001db4: b580 push {r7, lr} 10001db6: b084 sub sp, #16 10001db8: af00 add r7, sp, #0 10001dba: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the parameters */ assert_param(IS_RCC_PLL(pll2->PLLState)); if ((pll2->PLLState) != RCC_PLL_NONE) 10001dbc: 687b ldr r3, [r7, #4] 10001dbe: 681b ldr r3, [r3, #0] 10001dc0: 2b00 cmp r3, #0 10001dc2: f000 8171 beq.w 100020a8 { /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/ if (!__IS_PLL2_IN_USE()) /* If not used then */ 10001dc6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001dca: 6a5b ldr r3, [r3, #36] @ 0x24 10001dcc: f003 0307 and.w r3, r3, #7 10001dd0: 2b02 cmp r3, #2 10001dd2: d108 bne.n 10001de6 10001dd4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001dd8: 6a5b ldr r3, [r3, #36] @ 0x24 10001dda: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001dde: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001de2: f000 815f beq.w 100020a4 { if ((pll2->PLLState) == RCC_PLL_ON) 10001de6: 687b ldr r3, [r7, #4] 10001de8: 681b ldr r3, [r3, #0] 10001dea: 2b02 cmp r3, #2 10001dec: f040 8130 bne.w 10002050 assert_param(IS_RCC_PLLP2_VALUE(pll2->PLLP)); assert_param(IS_RCC_PLLQ2_VALUE(pll2->PLLQ)); assert_param(IS_RCC_PLLR2_VALUE(pll2->PLLR)); /* Check that PLL2 OSC clock source is already set */ if ((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) && 10001df0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001df4: 6a9b ldr r3, [r3, #40] @ 0x28 10001df6: f003 0303 and.w r3, r3, #3 10001dfa: 2b00 cmp r3, #0 10001dfc: d008 beq.n 10001e10 (__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSE)) 10001dfe: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e02: 6a9b ldr r3, [r3, #40] @ 0x28 10001e04: f003 0303 and.w r3, r3, #3 if ((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) && 10001e08: 2b01 cmp r3, #1 10001e0a: d001 beq.n 10001e10 { return HAL_ERROR; 10001e0c: 2301 movs r3, #1 10001e0e: e14c b.n 100020aa } /*Disable the post-dividers*/ __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); 10001e10: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e14: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10001e18: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001e1c: f023 0370 bic.w r3, r3, #112 @ 0x70 10001e20: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Disable the main PLL. */ __HAL_RCC_PLL2_DISABLE(); 10001e24: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e28: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10001e2c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001e30: f023 0301 bic.w r3, r3, #1 10001e34: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10001e38: f7fe fade bl 100003f8 10001e3c: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 10001e3e: e008 b.n 10001e52 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10001e40: f7fe fada bl 100003f8 10001e44: 4602 mov r2, r0 10001e46: 68fb ldr r3, [r7, #12] 10001e48: 1ad3 subs r3, r2, r3 10001e4a: 2b64 cmp r3, #100 @ 0x64 10001e4c: d901 bls.n 10001e52 { return HAL_TIMEOUT; 10001e4e: 2303 movs r3, #3 10001e50: e12b b.n 100020aa while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 10001e52: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e56: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10001e5a: f003 0302 and.w r3, r3, #2 10001e5e: 2b02 cmp r3, #2 10001e60: d0ee beq.n 10001e40 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN) -Fractional Division Enable (PLLxFRACNEN) -Fractional Division factor (FRACNx)*/ /* Do not change pll src if already in use */ if (__IS_PLL1_IN_USE()) 10001e62: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e66: 6a1b ldr r3, [r3, #32] 10001e68: f003 0303 and.w r3, r3, #3 10001e6c: 2b02 cmp r3, #2 10001e6e: d107 bne.n 10001e80 10001e70: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e74: 6a1b ldr r3, [r3, #32] 10001e76: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001e7a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001e7e: d00e beq.n 10001e9e 10001e80: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e84: 6a1b ldr r3, [r3, #32] 10001e86: f003 0303 and.w r3, r3, #3 10001e8a: 2b03 cmp r3, #3 10001e8c: d112 bne.n 10001eb4 10001e8e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001e92: 6a1b ldr r3, [r3, #32] 10001e94: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10001e98: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10001e9c: d10a bne.n 10001eb4 { if (pll2->PLLSource != __HAL_RCC_GET_PLL12_SOURCE()) 10001e9e: 687b ldr r3, [r7, #4] 10001ea0: 685a ldr r2, [r3, #4] 10001ea2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001ea6: 6a9b ldr r3, [r3, #40] @ 0x28 10001ea8: f003 0303 and.w r3, r3, #3 10001eac: 429a cmp r2, r3 10001eae: d00c beq.n 10001eca { return HAL_ERROR; 10001eb0: 2301 movs r3, #1 10001eb2: e0fa b.n 100020aa } } else { /* Configure PLL1 and PLL2 clock source */ __HAL_RCC_PLL12_SOURCE(pll2->PLLSource); 10001eb4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001eb8: 6a9b ldr r3, [r3, #40] @ 0x28 10001eba: f023 0203 bic.w r2, r3, #3 10001ebe: 687b ldr r3, [r7, #4] 10001ec0: 685b ldr r3, [r3, #4] 10001ec2: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001ec6: 4313 orrs r3, r2 10001ec8: 628b str r3, [r1, #40] @ 0x28 } /* Configure the PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG( 10001eca: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001ece: f8d3 2098 ldr.w r2, [r3, #152] @ 0x98 10001ed2: 4b78 ldr r3, [pc, #480] @ (100020b4 ) 10001ed4: 4013 ands r3, r2 10001ed6: 687a ldr r2, [r7, #4] 10001ed8: 68d2 ldr r2, [r2, #12] 10001eda: 1e51 subs r1, r2, #1 10001edc: 687a ldr r2, [r7, #4] 10001ede: 6892 ldr r2, [r2, #8] 10001ee0: 3a01 subs r2, #1 10001ee2: 0412 lsls r2, r2, #16 10001ee4: 430a orrs r2, r1 10001ee6: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001eea: 4313 orrs r3, r2 10001eec: f8c1 3098 str.w r3, [r1, #152] @ 0x98 10001ef0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001ef4: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 10001ef8: f023 137f bic.w r3, r3, #8323199 @ 0x7f007f 10001efc: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 10001f00: 687a ldr r2, [r7, #4] 10001f02: 6912 ldr r2, [r2, #16] 10001f04: 1e51 subs r1, r2, #1 10001f06: 687a ldr r2, [r7, #4] 10001f08: 6952 ldr r2, [r2, #20] 10001f0a: 3a01 subs r2, #1 10001f0c: 0212 lsls r2, r2, #8 10001f0e: 4311 orrs r1, r2 10001f10: 687a ldr r2, [r7, #4] 10001f12: 6992 ldr r2, [r2, #24] 10001f14: 3a01 subs r2, #1 10001f16: 0412 lsls r2, r2, #16 10001f18: 430a orrs r2, r1 10001f1a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001f1e: 4313 orrs r3, r2 10001f20: f8c1 309c str.w r3, [r1, #156] @ 0x9c pll2->PLLQ, pll2->PLLR); /* Configure the Fractional Divider */ __HAL_RCC_PLL2FRACV_DISABLE(); //Set FRACLE to ‘0’ 10001f24: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001f28: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 10001f2c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001f30: f423 3380 bic.w r3, r3, #65536 @ 0x10000 10001f34: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */ if ((pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll2->PLLMODE == RCC_PLL_INTEGER)) 10001f38: 687b ldr r3, [r7, #4] 10001f3a: 6a5b ldr r3, [r3, #36] @ 0x24 10001f3c: 2b02 cmp r3, #2 10001f3e: d003 beq.n 10001f48 10001f40: 687b ldr r3, [r7, #4] 10001f42: 6a5b ldr r3, [r3, #36] @ 0x24 10001f44: 2b00 cmp r3, #0 10001f46: d10c bne.n 10001f62 { /* Do not use the fractional divider */ __HAL_RCC_PLL2FRACV_CONFIG(0); //Set FRACV to '0' 10001f48: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001f4c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 10001f50: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001f54: f423 437f bic.w r3, r3, #65280 @ 0xff00 10001f58: f023 03f8 bic.w r3, r3, #248 @ 0xf8 10001f5c: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 10001f60: e00f b.n 10001f82 } else { /* Configure PLL PLL2FRACV in fractional mode*/ __HAL_RCC_PLL2FRACV_CONFIG(pll2->PLLFRACV); 10001f62: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001f66: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 10001f6a: f423 437f bic.w r3, r3, #65280 @ 0xff00 10001f6e: f023 03f8 bic.w r3, r3, #248 @ 0xf8 10001f72: 687a ldr r2, [r7, #4] 10001f74: 6a12 ldr r2, [r2, #32] 10001f76: 00d2 lsls r2, r2, #3 10001f78: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001f7c: 4313 orrs r3, r2 10001f7e: f8c1 30a0 str.w r3, [r1, #160] @ 0xa0 } __HAL_RCC_PLL2FRACV_ENABLE(); //Set FRACLE to ‘1’ 10001f82: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001f86: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 10001f8a: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001f8e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 10001f92: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 /* Configure the Spread Control */ if (pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) 10001f96: 687b ldr r3, [r7, #4] 10001f98: 6a5b ldr r3, [r3, #36] @ 0x24 10001f9a: 2b02 cmp r3, #2 10001f9c: d124 bne.n 10001fe8 assert_param(IS_RCC_SSCG_MODE(pll2->SSCG_MODE)); assert_param(IS_RCC_RPDFN_DIS(pll2->RPDFN_DIS)); assert_param(IS_RCC_TPDFN_DIS(pll2->TPDFN_DIS)); assert_param(IS_RCC_MOD_PER(pll2->MOD_PER)); __HAL_RCC_PLL2CSGCONFIG(pll2->MOD_PER, pll2->TPDFN_DIS, pll2->RPDFN_DIS, 10001f9e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001fa2: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 10001fa6: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 10001faa: 687b ldr r3, [r7, #4] 10001fac: 6a99 ldr r1, [r3, #40] @ 0x28 10001fae: 687b ldr r3, [r7, #4] 10001fb0: 6b1b ldr r3, [r3, #48] @ 0x30 10001fb2: 4319 orrs r1, r3 10001fb4: 687b ldr r3, [r7, #4] 10001fb6: 6adb ldr r3, [r3, #44] @ 0x2c 10001fb8: 4319 orrs r1, r3 10001fba: 687b ldr r3, [r7, #4] 10001fbc: 6b5b ldr r3, [r3, #52] @ 0x34 10001fbe: 4319 orrs r1, r3 10001fc0: 687b ldr r3, [r7, #4] 10001fc2: 6b9b ldr r3, [r3, #56] @ 0x38 10001fc4: 041b lsls r3, r3, #16 10001fc6: 430b orrs r3, r1 10001fc8: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10001fcc: 4313 orrs r3, r2 10001fce: f8c1 30a4 str.w r3, [r1, #164] @ 0xa4 pll2->SSCG_MODE, pll2->INC_STEP); __HAL_RCC_PLL2_SSMODE_ENABLE(); 10001fd2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001fd6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10001fda: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001fde: f043 0304 orr.w r3, r3, #4 10001fe2: f8c2 3094 str.w r3, [r2, #148] @ 0x94 10001fe6: e009 b.n 10001ffc } else { __HAL_RCC_PLL2_SSMODE_DISABLE(); 10001fe8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10001fec: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10001ff0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10001ff4: f023 0304 bic.w r3, r3, #4 10001ff8: f8c2 3094 str.w r3, [r2, #148] @ 0x94 } /* Enable the PLL2. */ __HAL_RCC_PLL2_ENABLE(); 10001ffc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002000: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10002004: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002008: f043 0301 orr.w r3, r3, #1 1000200c: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10002010: f7fe f9f2 bl 100003f8 10002014: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 10002016: e008 b.n 1000202a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002018: f7fe f9ee bl 100003f8 1000201c: 4602 mov r2, r0 1000201e: 68fb ldr r3, [r7, #12] 10002020: 1ad3 subs r3, r2, r3 10002022: 2b64 cmp r3, #100 @ 0x64 10002024: d901 bls.n 1000202a { return HAL_TIMEOUT; 10002026: 2303 movs r3, #3 10002028: e03f b.n 100020aa while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) 1000202a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000202e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10002032: f003 0302 and.w r3, r3, #2 10002036: 2b02 cmp r3, #2 10002038: d1ee bne.n 10002018 } } /*Enable the post-dividers*/ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); 1000203a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000203e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10002042: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002046: f043 0370 orr.w r3, r3, #112 @ 0x70 1000204a: f8c2 3094 str.w r3, [r2, #148] @ 0x94 if ((pll2->PLLState) == RCC_PLL_ON) 1000204e: e02b b.n 100020a8 } else { /*Disable the post-dividers*/ __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR); 10002050: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002054: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 10002058: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 1000205c: f023 0370 bic.w r3, r3, #112 @ 0x70 10002060: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Disable the PLL2. */ __HAL_RCC_PLL2_DISABLE(); 10002064: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002068: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 1000206c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002070: f023 0301 bic.w r3, r3, #1 10002074: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10002078: f7fe f9be bl 100003f8 1000207c: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 1000207e: e008 b.n 10002092 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002080: f7fe f9ba bl 100003f8 10002084: 4602 mov r2, r0 10002086: 68fb ldr r3, [r7, #12] 10002088: 1ad3 subs r3, r2, r3 1000208a: 2b64 cmp r3, #100 @ 0x64 1000208c: d901 bls.n 10002092 { return HAL_TIMEOUT; 1000208e: 2303 movs r3, #3 10002090: e00b b.n 100020aa while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) 10002092: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002096: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 1000209a: f003 0302 and.w r3, r3, #2 1000209e: 2b02 cmp r3, #2 100020a0: d0ee beq.n 10002080 if ((pll2->PLLState) == RCC_PLL_ON) 100020a2: e001 b.n 100020a8 } } } else { return HAL_ERROR; 100020a4: 2301 movs r3, #1 100020a6: e000 b.n 100020aa } } return HAL_OK; 100020a8: 2300 movs r3, #0 } 100020aa: 4618 mov r0, r3 100020ac: 3710 adds r7, #16 100020ae: 46bd mov sp, r7 100020b0: bd80 pop {r7, pc} 100020b2: bf00 nop 100020b4: ffc0fe00 .word 0xffc0fe00 100020b8 : * @param pll3: pointer to a RCC_PLLInitTypeDef structure * * @retval HAL status */ HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3) { 100020b8: b580 push {r7, lr} 100020ba: b084 sub sp, #16 100020bc: af00 add r7, sp, #0 100020be: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the parameters */ assert_param(IS_RCC_PLL(pll3->PLLState)); if ((pll3->PLLState) != RCC_PLL_NONE) 100020c0: 687b ldr r3, [r7, #4] 100020c2: 681b ldr r3, [r3, #0] 100020c4: 2b00 cmp r3, #0 100020c6: f000 815a beq.w 1000237e { /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/ if (!__IS_PLL3_IN_USE()) /* If not used then*/ 100020ca: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100020ce: 6c9b ldr r3, [r3, #72] @ 0x48 100020d0: f003 0303 and.w r3, r3, #3 100020d4: 2b03 cmp r3, #3 100020d6: d108 bne.n 100020ea 100020d8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100020dc: 6c9b ldr r3, [r3, #72] @ 0x48 100020de: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 100020e2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 100020e6: f000 8148 beq.w 1000237a { if ((pll3->PLLState) == RCC_PLL_ON) 100020ea: 687b ldr r3, [r7, #4] 100020ec: 681b ldr r3, [r3, #0] 100020ee: 2b02 cmp r3, #2 100020f0: f040 8119 bne.w 10002326 assert_param(IS_RCC_PLLP3_VALUE(pll3->PLLP)); assert_param(IS_RCC_PLLQ3_VALUE(pll3->PLLQ)); assert_param(IS_RCC_PLLR3_VALUE(pll3->PLLR)); /*Disable the post-dividers*/ __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR); 100020f4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100020f8: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 100020fc: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002100: f023 0370 bic.w r3, r3, #112 @ 0x70 10002104: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 /* Disable the main PLL. */ __HAL_RCC_PLL3_DISABLE(); 10002108: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000210c: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10002110: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002114: f023 0301 bic.w r3, r3, #1 10002118: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000211c: f7fe f96c bl 100003f8 10002120: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET) 10002122: e008 b.n 10002136 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002124: f7fe f968 bl 100003f8 10002128: 4602 mov r2, r0 1000212a: 68fb ldr r3, [r7, #12] 1000212c: 1ad3 subs r3, r2, r3 1000212e: 2b64 cmp r3, #100 @ 0x64 10002130: d901 bls.n 10002136 { return HAL_TIMEOUT; 10002132: 2303 movs r3, #3 10002134: e124 b.n 10002380 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET) 10002136: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000213a: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 1000213e: f003 0302 and.w r3, r3, #2 10002142: 2b02 cmp r3, #2 10002144: d0ee beq.n 10002124 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN) -Fractional Division Enable (PLLxFRACNEN) -Fractional Division factor (FRACNx)*/ /* Configure PLL3 clock source */ __HAL_RCC_PLL3_SOURCE(pll3->PLLSource); 10002146: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000214a: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 1000214e: f023 0203 bic.w r2, r3, #3 10002152: 687b ldr r3, [r7, #4] 10002154: 685b ldr r3, [r3, #4] 10002156: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000215a: 4313 orrs r3, r2 1000215c: f8c1 3820 str.w r3, [r1, #2080] @ 0x820 /* Wait till PLL SOURCE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3SRCRDY) == RESET) 10002160: e008 b.n 10002174 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002162: f7fe f949 bl 100003f8 10002166: 4602 mov r2, r0 10002168: 68fb ldr r3, [r7, #12] 1000216a: 1ad3 subs r3, r2, r3 1000216c: 2b64 cmp r3, #100 @ 0x64 1000216e: d901 bls.n 10002174 { return HAL_TIMEOUT; 10002170: 2303 movs r3, #3 10002172: e105 b.n 10002380 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3SRCRDY) == RESET) 10002174: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002178: f8d3 3820 ldr.w r3, [r3, #2080] @ 0x820 1000217c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10002180: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10002184: d1ed bne.n 10002162 } } /* Select PLL3 input reference frequency range */ __HAL_RCC_PLL3_IFRANGE(pll3->PLLRGE) ; 10002186: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000218a: f8d3 3884 ldr.w r3, [r3, #2180] @ 0x884 1000218e: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 10002192: 687b ldr r3, [r7, #4] 10002194: 69db ldr r3, [r3, #28] 10002196: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000219a: 4313 orrs r3, r2 1000219c: f8c1 3884 str.w r3, [r1, #2180] @ 0x884 /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG( 100021a0: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100021a4: f8d3 2884 ldr.w r2, [r3, #2180] @ 0x884 100021a8: 4b77 ldr r3, [pc, #476] @ (10002388 ) 100021aa: 4013 ands r3, r2 100021ac: 687a ldr r2, [r7, #4] 100021ae: 68d2 ldr r2, [r2, #12] 100021b0: 1e51 subs r1, r2, #1 100021b2: 687a ldr r2, [r7, #4] 100021b4: 6892 ldr r2, [r2, #8] 100021b6: 3a01 subs r2, #1 100021b8: 0412 lsls r2, r2, #16 100021ba: 430a orrs r2, r1 100021bc: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100021c0: 4313 orrs r3, r2 100021c2: f8c1 3884 str.w r3, [r1, #2180] @ 0x884 100021c6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100021ca: f8d3 3888 ldr.w r3, [r3, #2184] @ 0x888 100021ce: f023 137f bic.w r3, r3, #8323199 @ 0x7f007f 100021d2: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 100021d6: 687a ldr r2, [r7, #4] 100021d8: 6912 ldr r2, [r2, #16] 100021da: 1e51 subs r1, r2, #1 100021dc: 687a ldr r2, [r7, #4] 100021de: 6952 ldr r2, [r2, #20] 100021e0: 3a01 subs r2, #1 100021e2: 0212 lsls r2, r2, #8 100021e4: 4311 orrs r1, r2 100021e6: 687a ldr r2, [r7, #4] 100021e8: 6992 ldr r2, [r2, #24] 100021ea: 3a01 subs r2, #1 100021ec: 0412 lsls r2, r2, #16 100021ee: 430a orrs r2, r1 100021f0: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100021f4: 4313 orrs r3, r2 100021f6: f8c1 3888 str.w r3, [r1, #2184] @ 0x888 pll3->PLLP, pll3->PLLQ, pll3->PLLR); /* Configure the Fractional Divider */ __HAL_RCC_PLL3FRACV_DISABLE(); //Set FRACLE to ‘0’ 100021fa: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100021fe: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10002202: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002206: f423 3380 bic.w r3, r3, #65536 @ 0x10000 1000220a: f8c2 388c str.w r3, [r2, #2188] @ 0x88c /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */ if ((pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll3->PLLMODE == RCC_PLL_INTEGER)) 1000220e: 687b ldr r3, [r7, #4] 10002210: 6a5b ldr r3, [r3, #36] @ 0x24 10002212: 2b02 cmp r3, #2 10002214: d003 beq.n 1000221e 10002216: 687b ldr r3, [r7, #4] 10002218: 6a5b ldr r3, [r3, #36] @ 0x24 1000221a: 2b00 cmp r3, #0 1000221c: d10c bne.n 10002238 { /* Do not use the fractional divider */ __HAL_RCC_PLL3FRACV_CONFIG(0); //Set FRACV to '0' 1000221e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002222: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10002226: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 1000222a: f423 437f bic.w r3, r3, #65280 @ 0xff00 1000222e: f023 03f8 bic.w r3, r3, #248 @ 0xf8 10002232: f8c2 388c str.w r3, [r2, #2188] @ 0x88c 10002236: e00f b.n 10002258 } else { /* Configure PLL PLL3FRACV in fractional mode*/ __HAL_RCC_PLL3FRACV_CONFIG(pll3->PLLFRACV); 10002238: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000223c: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10002240: f423 437f bic.w r3, r3, #65280 @ 0xff00 10002244: f023 03f8 bic.w r3, r3, #248 @ 0xf8 10002248: 687a ldr r2, [r7, #4] 1000224a: 6a12 ldr r2, [r2, #32] 1000224c: 00d2 lsls r2, r2, #3 1000224e: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10002252: 4313 orrs r3, r2 10002254: f8c1 388c str.w r3, [r1, #2188] @ 0x88c } __HAL_RCC_PLL3FRACV_ENABLE(); //Set FRACLE to ‘1’ 10002258: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000225c: f8d3 388c ldr.w r3, [r3, #2188] @ 0x88c 10002260: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002264: f443 3380 orr.w r3, r3, #65536 @ 0x10000 10002268: f8c2 388c str.w r3, [r2, #2188] @ 0x88c /* Configure the Spread Control */ if (pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) 1000226c: 687b ldr r3, [r7, #4] 1000226e: 6a5b ldr r3, [r3, #36] @ 0x24 10002270: 2b02 cmp r3, #2 10002272: d124 bne.n 100022be assert_param(IS_RCC_SSCG_MODE(pll3->SSCG_MODE)); assert_param(IS_RCC_RPDFN_DIS(pll3->RPDFN_DIS)); assert_param(IS_RCC_TPDFN_DIS(pll3->TPDFN_DIS)); assert_param(IS_RCC_MOD_PER(pll3->MOD_PER)); __HAL_RCC_PLL3CSGCONFIG(pll3->MOD_PER, pll3->TPDFN_DIS, pll3->RPDFN_DIS, 10002274: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002278: f8d3 3890 ldr.w r3, [r3, #2192] @ 0x890 1000227c: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 10002280: 687b ldr r3, [r7, #4] 10002282: 6a99 ldr r1, [r3, #40] @ 0x28 10002284: 687b ldr r3, [r7, #4] 10002286: 6b1b ldr r3, [r3, #48] @ 0x30 10002288: 4319 orrs r1, r3 1000228a: 687b ldr r3, [r7, #4] 1000228c: 6adb ldr r3, [r3, #44] @ 0x2c 1000228e: 4319 orrs r1, r3 10002290: 687b ldr r3, [r7, #4] 10002292: 6b5b ldr r3, [r3, #52] @ 0x34 10002294: 4319 orrs r1, r3 10002296: 687b ldr r3, [r7, #4] 10002298: 6b9b ldr r3, [r3, #56] @ 0x38 1000229a: 041b lsls r3, r3, #16 1000229c: 430b orrs r3, r1 1000229e: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100022a2: 4313 orrs r3, r2 100022a4: f8c1 3890 str.w r3, [r1, #2192] @ 0x890 pll3->SSCG_MODE, pll3->INC_STEP); __HAL_RCC_PLL3_SSMODE_ENABLE(); 100022a8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100022ac: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 100022b0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100022b4: f043 0304 orr.w r3, r3, #4 100022b8: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 100022bc: e009 b.n 100022d2 } else { __HAL_RCC_PLL3_SSMODE_DISABLE(); 100022be: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100022c2: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 100022c6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100022ca: f023 0304 bic.w r3, r3, #4 100022ce: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 } /* Enable the PLL3. */ __HAL_RCC_PLL3_ENABLE(); 100022d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100022d6: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 100022da: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100022de: f043 0301 orr.w r3, r3, #1 100022e2: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 /* Get Start Tick*/ tickstart = HAL_GetTick(); 100022e6: f7fe f887 bl 100003f8 100022ea: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET) 100022ec: e008 b.n 10002300 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 100022ee: f7fe f883 bl 100003f8 100022f2: 4602 mov r2, r0 100022f4: 68fb ldr r3, [r7, #12] 100022f6: 1ad3 subs r3, r2, r3 100022f8: 2b64 cmp r3, #100 @ 0x64 100022fa: d901 bls.n 10002300 { return HAL_TIMEOUT; 100022fc: 2303 movs r3, #3 100022fe: e03f b.n 10002380 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET) 10002300: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002304: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10002308: f003 0302 and.w r3, r3, #2 1000230c: 2b02 cmp r3, #2 1000230e: d1ee bne.n 100022ee } } /* Enable the post-dividers */ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR); 10002310: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002314: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10002318: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 1000231c: f043 0370 orr.w r3, r3, #112 @ 0x70 10002320: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 if ((pll3->PLLState) == RCC_PLL_ON) 10002324: e02b b.n 1000237e } else { /*Disable the post-dividers*/ __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR); 10002326: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000232a: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 1000232e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002332: f023 0370 bic.w r3, r3, #112 @ 0x70 10002336: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 /* Disable the PLL3. */ __HAL_RCC_PLL3_DISABLE(); 1000233a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000233e: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10002342: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002346: f023 0301 bic.w r3, r3, #1 1000234a: f8c2 3880 str.w r3, [r2, #2176] @ 0x880 /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000234e: f7fe f853 bl 100003f8 10002352: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET) 10002354: e008 b.n 10002368 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002356: f7fe f84f bl 100003f8 1000235a: 4602 mov r2, r0 1000235c: 68fb ldr r3, [r7, #12] 1000235e: 1ad3 subs r3, r2, r3 10002360: 2b64 cmp r3, #100 @ 0x64 10002362: d901 bls.n 10002368 { return HAL_TIMEOUT; 10002364: 2303 movs r3, #3 10002366: e00b b.n 10002380 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET) 10002368: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000236c: f8d3 3880 ldr.w r3, [r3, #2176] @ 0x880 10002370: f003 0302 and.w r3, r3, #2 10002374: 2b02 cmp r3, #2 10002376: d0ee beq.n 10002356 if ((pll3->PLLState) == RCC_PLL_ON) 10002378: e001 b.n 1000237e } } } else { return HAL_ERROR; 1000237a: 2301 movs r3, #1 1000237c: e000 b.n 10002380 } } return HAL_OK; 1000237e: 2300 movs r3, #0 } 10002380: 4618 mov r0, r3 10002382: 3710 adds r7, #16 10002384: 46bd mov sp, r7 10002386: bd80 pop {r7, pc} 10002388: ffc0fe00 .word 0xffc0fe00 1000238c : * @param pll4: pointer to a RCC_PLLInitTypeDef structure * * @retval HAL status */ HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4) { 1000238c: b580 push {r7, lr} 1000238e: b084 sub sp, #16 10002390: af00 add r7, sp, #0 10002392: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the parameters */ assert_param(IS_RCC_PLL(pll4->PLLState)); if ((pll4->PLLState) != RCC_PLL_NONE) 10002394: 687b ldr r3, [r7, #4] 10002396: 681b ldr r3, [r3, #0] 10002398: 2b00 cmp r3, #0 1000239a: f000 8147 beq.w 1000262c { if ((pll4->PLLState) == RCC_PLL_ON) 1000239e: 687b ldr r3, [r7, #4] 100023a0: 681b ldr r3, [r3, #0] 100023a2: 2b02 cmp r3, #2 100023a4: f040 8119 bne.w 100025da assert_param(IS_RCC_PLLP4_VALUE(pll4->PLLP)); assert_param(IS_RCC_PLLQ4_VALUE(pll4->PLLQ)); assert_param(IS_RCC_PLLR4_VALUE(pll4->PLLR)); /*Disable the post-dividers*/ __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR); 100023a8: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100023ac: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100023b0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100023b4: f023 0370 bic.w r3, r3, #112 @ 0x70 100023b8: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 /* Disable the main PLL. */ __HAL_RCC_PLL4_DISABLE(); 100023bc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100023c0: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100023c4: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100023c8: f023 0301 bic.w r3, r3, #1 100023cc: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 /* Get Start Tick*/ tickstart = HAL_GetTick(); 100023d0: f7fe f812 bl 100003f8 100023d4: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET) 100023d6: e008 b.n 100023ea { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 100023d8: f7fe f80e bl 100003f8 100023dc: 4602 mov r2, r0 100023de: 68fb ldr r3, [r7, #12] 100023e0: 1ad3 subs r3, r2, r3 100023e2: 2b64 cmp r3, #100 @ 0x64 100023e4: d901 bls.n 100023ea { return HAL_TIMEOUT; 100023e6: 2303 movs r3, #3 100023e8: e121 b.n 1000262e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET) 100023ea: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100023ee: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100023f2: f003 0302 and.w r3, r3, #2 100023f6: 2b02 cmp r3, #2 100023f8: d0ee beq.n 100023d8 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN) -Fractional Division Enable (PLLxFRACNEN) -Fractional Division factor (FRACNx)*/ /* Configure PLL4 and PLL4 clock source */ __HAL_RCC_PLL4_SOURCE(pll4->PLLSource); 100023fa: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100023fe: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10002402: f023 0203 bic.w r2, r3, #3 10002406: 687b ldr r3, [r7, #4] 10002408: 685b ldr r3, [r3, #4] 1000240a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000240e: 4313 orrs r3, r2 10002410: f8c1 3824 str.w r3, [r1, #2084] @ 0x824 /* Wait till PLL SOURCE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4SRCRDY) == RESET) 10002414: e008 b.n 10002428 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 10002416: f7fd ffef bl 100003f8 1000241a: 4602 mov r2, r0 1000241c: 68fb ldr r3, [r7, #12] 1000241e: 1ad3 subs r3, r2, r3 10002420: 2b64 cmp r3, #100 @ 0x64 10002422: d901 bls.n 10002428 { return HAL_TIMEOUT; 10002424: 2303 movs r3, #3 10002426: e102 b.n 1000262e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4SRCRDY) == RESET) 10002428: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000242c: f8d3 3824 ldr.w r3, [r3, #2084] @ 0x824 10002430: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 10002434: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 10002438: d1ed bne.n 10002416 } } /* Select PLL4 input reference frequency range */ __HAL_RCC_PLL4_IFRANGE(pll4->PLLRGE) ; 1000243a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000243e: f8d3 3898 ldr.w r3, [r3, #2200] @ 0x898 10002442: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 10002446: 687b ldr r3, [r7, #4] 10002448: 69db ldr r3, [r3, #28] 1000244a: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 1000244e: 4313 orrs r3, r2 10002450: f8c1 3898 str.w r3, [r1, #2200] @ 0x898 /* Configure the PLL4 multiplication and division factors. */ __HAL_RCC_PLL4_CONFIG( 10002454: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002458: f8d3 2898 ldr.w r2, [r3, #2200] @ 0x898 1000245c: 4b76 ldr r3, [pc, #472] @ (10002638 ) 1000245e: 4013 ands r3, r2 10002460: 687a ldr r2, [r7, #4] 10002462: 68d2 ldr r2, [r2, #12] 10002464: 1e51 subs r1, r2, #1 10002466: 687a ldr r2, [r7, #4] 10002468: 6892 ldr r2, [r2, #8] 1000246a: 3a01 subs r2, #1 1000246c: 0412 lsls r2, r2, #16 1000246e: 430a orrs r2, r1 10002470: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10002474: 4313 orrs r3, r2 10002476: f8c1 3898 str.w r3, [r1, #2200] @ 0x898 1000247a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000247e: f8d3 389c ldr.w r3, [r3, #2204] @ 0x89c 10002482: f023 137f bic.w r3, r3, #8323199 @ 0x7f007f 10002486: f423 43fe bic.w r3, r3, #32512 @ 0x7f00 1000248a: 687a ldr r2, [r7, #4] 1000248c: 6912 ldr r2, [r2, #16] 1000248e: 1e51 subs r1, r2, #1 10002490: 687a ldr r2, [r7, #4] 10002492: 6952 ldr r2, [r2, #20] 10002494: 3a01 subs r2, #1 10002496: 0212 lsls r2, r2, #8 10002498: 4311 orrs r1, r2 1000249a: 687a ldr r2, [r7, #4] 1000249c: 6992 ldr r2, [r2, #24] 1000249e: 3a01 subs r2, #1 100024a0: 0412 lsls r2, r2, #16 100024a2: 430a orrs r2, r1 100024a4: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 100024a8: 4313 orrs r3, r2 100024aa: f8c1 389c str.w r3, [r1, #2204] @ 0x89c pll4->PLLP, pll4->PLLQ, pll4->PLLR); /* Configure the Fractional Divider */ __HAL_RCC_PLL4FRACV_DISABLE(); //Set FRACLE to ‘0’ 100024ae: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100024b2: f8d3 38a0 ldr.w r3, [r3, #2208] @ 0x8a0 100024b6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100024ba: f423 3380 bic.w r3, r3, #65536 @ 0x10000 100024be: f8c2 38a0 str.w r3, [r2, #2208] @ 0x8a0 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */ if ((pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll4->PLLMODE == RCC_PLL_INTEGER)) 100024c2: 687b ldr r3, [r7, #4] 100024c4: 6a5b ldr r3, [r3, #36] @ 0x24 100024c6: 2b02 cmp r3, #2 100024c8: d003 beq.n 100024d2 100024ca: 687b ldr r3, [r7, #4] 100024cc: 6a5b ldr r3, [r3, #36] @ 0x24 100024ce: 2b00 cmp r3, #0 100024d0: d10c bne.n 100024ec { /* Do not use the fractional divider */ __HAL_RCC_PLL4FRACV_CONFIG(0); //Set FRACV to '0' 100024d2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100024d6: f8d3 38a0 ldr.w r3, [r3, #2208] @ 0x8a0 100024da: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100024de: f423 437f bic.w r3, r3, #65280 @ 0xff00 100024e2: f023 03f8 bic.w r3, r3, #248 @ 0xf8 100024e6: f8c2 38a0 str.w r3, [r2, #2208] @ 0x8a0 100024ea: e00f b.n 1000250c } else { /* Configure PLL PLL4FRACV in fractional mode*/ __HAL_RCC_PLL4FRACV_CONFIG(pll4->PLLFRACV); 100024ec: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100024f0: f8d3 38a0 ldr.w r3, [r3, #2208] @ 0x8a0 100024f4: f423 437f bic.w r3, r3, #65280 @ 0xff00 100024f8: f023 03f8 bic.w r3, r3, #248 @ 0xf8 100024fc: 687a ldr r2, [r7, #4] 100024fe: 6a12 ldr r2, [r2, #32] 10002500: 00d2 lsls r2, r2, #3 10002502: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10002506: 4313 orrs r3, r2 10002508: f8c1 38a0 str.w r3, [r1, #2208] @ 0x8a0 } __HAL_RCC_PLL4FRACV_ENABLE(); //Set FRACLE to ‘1’ 1000250c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002510: f8d3 38a0 ldr.w r3, [r3, #2208] @ 0x8a0 10002514: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002518: f443 3380 orr.w r3, r3, #65536 @ 0x10000 1000251c: f8c2 38a0 str.w r3, [r2, #2208] @ 0x8a0 /* Configure the Spread Control */ if (pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) 10002520: 687b ldr r3, [r7, #4] 10002522: 6a5b ldr r3, [r3, #36] @ 0x24 10002524: 2b02 cmp r3, #2 10002526: d124 bne.n 10002572 assert_param(IS_RCC_SSCG_MODE(pll4->SSCG_MODE)); assert_param(IS_RCC_RPDFN_DIS(pll4->RPDFN_DIS)); assert_param(IS_RCC_TPDFN_DIS(pll4->TPDFN_DIS)); assert_param(IS_RCC_MOD_PER(pll4->MOD_PER)); __HAL_RCC_PLL4CSGCONFIG(pll4->MOD_PER, pll4->TPDFN_DIS, pll4->RPDFN_DIS, 10002528: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000252c: f8d3 38a4 ldr.w r3, [r3, #2212] @ 0x8a4 10002530: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 10002534: 687b ldr r3, [r7, #4] 10002536: 6a99 ldr r1, [r3, #40] @ 0x28 10002538: 687b ldr r3, [r7, #4] 1000253a: 6b1b ldr r3, [r3, #48] @ 0x30 1000253c: 4319 orrs r1, r3 1000253e: 687b ldr r3, [r7, #4] 10002540: 6adb ldr r3, [r3, #44] @ 0x2c 10002542: 4319 orrs r1, r3 10002544: 687b ldr r3, [r7, #4] 10002546: 6b5b ldr r3, [r3, #52] @ 0x34 10002548: 4319 orrs r1, r3 1000254a: 687b ldr r3, [r7, #4] 1000254c: 6b9b ldr r3, [r3, #56] @ 0x38 1000254e: 041b lsls r3, r3, #16 10002550: 430b orrs r3, r1 10002552: f04f 41a0 mov.w r1, #1342177280 @ 0x50000000 10002556: 4313 orrs r3, r2 10002558: f8c1 38a4 str.w r3, [r1, #2212] @ 0x8a4 pll4->SSCG_MODE, pll4->INC_STEP); __HAL_RCC_PLL4_SSMODE_ENABLE(); 1000255c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002560: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10002564: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002568: f043 0304 orr.w r3, r3, #4 1000256c: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 10002570: e009 b.n 10002586 } else { __HAL_RCC_PLL4_SSMODE_DISABLE(); 10002572: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002576: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 1000257a: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 1000257e: f023 0304 bic.w r3, r3, #4 10002582: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 } /* Enable the PLL4. */ __HAL_RCC_PLL4_ENABLE(); 10002586: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 1000258a: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 1000258e: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 10002592: f043 0301 orr.w r3, r3, #1 10002596: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 /* Get Start Tick*/ tickstart = HAL_GetTick(); 1000259a: f7fd ff2d bl 100003f8 1000259e: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) == RESET) 100025a0: e008 b.n 100025b4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 100025a2: f7fd ff29 bl 100003f8 100025a6: 4602 mov r2, r0 100025a8: 68fb ldr r3, [r7, #12] 100025aa: 1ad3 subs r3, r2, r3 100025ac: 2b64 cmp r3, #100 @ 0x64 100025ae: d901 bls.n 100025b4 { return HAL_TIMEOUT; 100025b0: 2303 movs r3, #3 100025b2: e03c b.n 1000262e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) == RESET) 100025b4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100025b8: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100025bc: f003 0302 and.w r3, r3, #2 100025c0: 2b02 cmp r3, #2 100025c2: d1ee bne.n 100025a2 } } /* Enable PLL4P Clock output. */ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR); 100025c4: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100025c8: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100025cc: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100025d0: f043 0370 orr.w r3, r3, #112 @ 0x70 100025d4: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 100025d8: e028 b.n 1000262c } else { /*Disable the post-dividers*/ __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR); 100025da: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100025de: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100025e2: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100025e6: f023 0370 bic.w r3, r3, #112 @ 0x70 100025ea: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 /* Disable the PLL4. */ __HAL_RCC_PLL4_DISABLE(); 100025ee: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 100025f2: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 100025f6: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 100025fa: f023 0301 bic.w r3, r3, #1 100025fe: f8c2 3894 str.w r3, [r2, #2196] @ 0x894 /* Get Start Tick*/ tickstart = HAL_GetTick(); 10002602: f7fd fef9 bl 100003f8 10002606: 60f8 str r0, [r7, #12] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET) 10002608: e008 b.n 1000261c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 1000260a: f7fd fef5 bl 100003f8 1000260e: 4602 mov r2, r0 10002610: 68fb ldr r3, [r7, #12] 10002612: 1ad3 subs r3, r2, r3 10002614: 2b64 cmp r3, #100 @ 0x64 10002616: d901 bls.n 1000261c { return HAL_TIMEOUT; 10002618: 2303 movs r3, #3 1000261a: e008 b.n 1000262e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET) 1000261c: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 10002620: f8d3 3894 ldr.w r3, [r3, #2196] @ 0x894 10002624: f003 0302 and.w r3, r3, #2 10002628: 2b02 cmp r3, #2 1000262a: d0ee beq.n 1000260a } } } } return HAL_OK; 1000262c: 2300 movs r3, #0 } 1000262e: 4618 mov r0, r3 10002630: 3710 adds r7, #16 10002632: 46bd mov sp, r7 10002634: bd80 pop {r7, pc} 10002636: bf00 nop 10002638: ffc0fe00 .word 0xffc0fe00 1000263c : 1000263c: 4402 add r2, r0 1000263e: 4603 mov r3, r0 10002640: 4293 cmp r3, r2 10002642: d100 bne.n 10002646 10002644: 4770 bx lr 10002646: f803 1b01 strb.w r1, [r3], #1 1000264a: e7f9 b.n 10002640 1000264c <__libc_init_array>: 1000264c: b570 push {r4, r5, r6, lr} 1000264e: 4d0d ldr r5, [pc, #52] @ (10002684 <__libc_init_array+0x38>) 10002650: 4c0d ldr r4, [pc, #52] @ (10002688 <__libc_init_array+0x3c>) 10002652: 1b64 subs r4, r4, r5 10002654: 10a4 asrs r4, r4, #2 10002656: 2600 movs r6, #0 10002658: 42a6 cmp r6, r4 1000265a: d109 bne.n 10002670 <__libc_init_array+0x24> 1000265c: 4d0b ldr r5, [pc, #44] @ (1000268c <__libc_init_array+0x40>) 1000265e: 4c0c ldr r4, [pc, #48] @ (10002690 <__libc_init_array+0x44>) 10002660: f000 f818 bl 10002694 <_init> 10002664: 1b64 subs r4, r4, r5 10002666: 10a4 asrs r4, r4, #2 10002668: 2600 movs r6, #0 1000266a: 42a6 cmp r6, r4 1000266c: d105 bne.n 1000267a <__libc_init_array+0x2e> 1000266e: bd70 pop {r4, r5, r6, pc} 10002670: f855 3b04 ldr.w r3, [r5], #4 10002674: 4798 blx r3 10002676: 3601 adds r6, #1 10002678: e7ee b.n 10002658 <__libc_init_array+0xc> 1000267a: f855 3b04 ldr.w r3, [r5], #4 1000267e: 4798 blx r3 10002680: 3601 adds r6, #1 10002682: e7f2 b.n 1000266a <__libc_init_array+0x1e> 10002684: 100026fc .word 0x100026fc 10002688: 100026fc .word 0x100026fc 1000268c: 100026fc .word 0x100026fc 10002690: 10002700 .word 0x10002700 10002694 <_init>: 10002694: b5f8 push {r3, r4, r5, r6, r7, lr} 10002696: bf00 nop 10002698: bcf8 pop {r3, r4, r5, r6, r7} 1000269a: bc08 pop {r3} 1000269c: 469e mov lr, r3 1000269e: 4770 bx lr 100026a0 <_fini>: 100026a0: b5f8 push {r3, r4, r5, r6, r7, lr} 100026a2: bf00 nop 100026a4: bcf8 pop {r3, r4, r5, r6, r7} 100026a6: bc08 pop {r3} 100026a8: 469e mov lr, r3 100026aa: 4770 bx lr Disassembly of section .startup_copro_fw.Reset_Handler: 100026ac : ldr sp, =_estack /* set stack pointer */ 100026ac: f8df d034 ldr.w sp, [pc, #52] @ 100026e4 movs r1, #0 100026b0: 2100 movs r1, #0 b LoopCopyDataInit 100026b2: e003 b.n 100026bc 100026b4 : ldr r3, =_sidata 100026b4: 4b0c ldr r3, [pc, #48] @ (100026e8 ) ldr r3, [r3, r1] 100026b6: 585b ldr r3, [r3, r1] str r3, [r0, r1] 100026b8: 5043 str r3, [r0, r1] adds r1, r1, #4 100026ba: 3104 adds r1, #4 100026bc : ldr r0, =_sdata 100026bc: 480b ldr r0, [pc, #44] @ (100026ec ) ldr r3, =_edata 100026be: 4b0c ldr r3, [pc, #48] @ (100026f0 ) adds r2, r0, r1 100026c0: 1842 adds r2, r0, r1 cmp r2, r3 100026c2: 429a cmp r2, r3 bcc CopyDataInit 100026c4: d3f6 bcc.n 100026b4 ldr r2, =_sbss 100026c6: 4a0b ldr r2, [pc, #44] @ (100026f4 ) b LoopFillZerobss 100026c8: e002 b.n 100026d0 100026ca : movs r3, #0 100026ca: 2300 movs r3, #0 str r3, [r2], #4 100026cc: f842 3b04 str.w r3, [r2], #4 100026d0 : ldr r3, = _ebss 100026d0: 4b09 ldr r3, [pc, #36] @ (100026f8 ) cmp r2, r3 100026d2: 429a cmp r2, r3 bcc FillZerobss 100026d4: d3f9 bcc.n 100026ca bl SystemInit 100026d6: f7fd fcb3 bl 10000040 bl __libc_init_array 100026da: f7ff ffb7 bl 1000264c <__libc_init_array> bl main 100026de: f7fd fcd5 bl 1000008c
100026e2 : b LoopForever 100026e2: e7fe b.n 100026e2 ldr sp, =_estack /* set stack pointer */ 100026e4: 10040000 .word 0x10040000 ldr r3, =_sidata 100026e8: 10002704 .word 0x10002704 ldr r0, =_sdata 100026ec: 10020000 .word 0x10020000 ldr r3, =_edata 100026f0: 1002000c .word 0x1002000c ldr r2, =_sbss 100026f4: 1002000c .word 0x1002000c ldr r3, = _ebss 100026f8: 1002002c .word 0x1002002c